Lines Matching refs:constrainOperandRegClass

305   Op0 = constrainOperandRegClass(II, Op0, 1);  in fastEmitInst_r()
327 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
328 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
354 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
510 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
583 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
661 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1050 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1124 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1261 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1298 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1429 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1634 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1654 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); in SelectSelect()
1655 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1663 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1764 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
2267 constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); in ARMEmitLibcall()
2409 constrainOperandRegClass(TII.get(CallOpc), CalleeReg, isThumb2 ? 2 : 0); in SelectCall()
2726 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR); in ARMEmitIntExt()
2981 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0); in ARMLowerPICELF()