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Searched refs:buildInstr (Results 1 – 25 of 28) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h367 MachineInstrBuilder buildInstr(unsigned Opcode) { in buildInstr() function
552 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut}, in buildUAdde()
560 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut}, in buildUSube()
568 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut}, in buildSAdde()
576 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut}, in buildSSube()
634 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src}); in buildBitcast()
1364 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src}); in buildFreeze()
1547 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0}); in buildCTLZ()
1557 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0}); in buildCTTZ()
1712 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src}); in buildAbs()
[all …]
H A DCSEMIRBuilder.h94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
H A DLegalizationArtifactCombiner.h79 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
179 Builder.buildInstr( in tryCombineSExt()
194 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineSExt()
337 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {}); in tryFoldImplicitDef()
905 Builder.buildInstr(ConvertOp, {DstRegs[k]}, {TmpRegs[k]}); in tryCombineUnmergeValues()
948 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineUnmergeValues()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp85 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
121 auto MIB = buildInstr(TargetOpcode::DBG_LABEL); in buildDbgLabel()
232 return buildInstr(TargetOpcode::G_BRJT) in buildBrJT()
363 auto MIB = buildInstr(Opcode); in buildLoadInstr()
393 auto MIB = buildInstr(TargetOpcode::G_STORE); in buildStore()
445 return buildInstr(ExtOp, Res, Op); in buildBoolExt()
469 return buildInstr(Opcode, Res, Op); in buildExtOrTrunc()
513 return buildInstr(Opcode, Dst, Src); in buildCast()
852 auto MIB = buildInstr(Opcode); in buildAtomicRMW()
945 return buildInstr(TargetOpcode::G_FENCE) in buildFence()
[all …]
H A DCSEMIRBuilder.cpp167 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() function in CSEMIRBuilder
219 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
223 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
240 MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
H A DLegalizerHelper.cpp1258 .buildInstr( in narrowScalar()
1357 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); in widenScalarDst()
1366 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); in narrowScalarDst()
4660 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, in fewerElementsVectorReductions()
5196 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, in narrowScalarAddSub()
5199 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, in narrowScalarAddSub()
5202 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, in narrowScalarAddSub()
5456 auto Inst = MIRBuilder.buildInstr( in narrowScalarBasic()
5944 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); in lowerRotateWithReverseRotate()
7253 MIRBuilder.buildInstr( in lowerDIVREM()
[all …]
H A DIRTranslator.cpp299 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
312 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
1459 MIRBuilder.buildInstr(Opcode, {Res}, {Op}); in translateCast()
1586 auto ICall = MIRBuilder.buildInstr(Opcode); in translateMemFunc()
1656 MIRBuilder.buildInstr( in translateOverflowIntrinsic()
1669 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale }); in translateFixedPointIntrinsic()
1785 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs, in translateSimpleIntrinsic()
2126 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, in translateKnownIntrinsic()
2164 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER) in translateKnownIntrinsic()
2224 auto Rdx = MIRBuilder.buildInstr( in translateKnownIntrinsic()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp399 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
412 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, in applyEXT()
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
717 B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane}); in applyDupLane()
739 B.buildInstr(AArch64::G_DUP, {MI.getOperand(0).getReg()}, in applyBuildVectorToDup()
868 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
876 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}) in getVectorFCMP()
883 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS}) in getVectorFCMP()
890 : MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS}) in getVectorFCMP()
897 : MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS}) in getVectorFCMP()
[all …]
H A DAArch64InstructionSelector.cpp1681 auto Bcc = MIB.buildInstr(AArch64::Bcc) in selectCompareBranch()
3411 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
3425 MIB.buildInstr(AArch64::MOVaddrJT, {DstReg}, {}) in selectJumpTable()
3456 MIB.buildInstr(getBLRCallOpcode(MF), {}, {Load}) in selectTLSGlobalValue()
3739 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp}); in selectVectorICmp()
4748 auto TBL1 = MIB.buildInstr( in selectShuffleVector()
5048 auto NewI = MIB.buildInstr( in selectIntrinsicWithSideEffects()
5057 MIB.buildInstr(AArch64::BRK, {}, {}).addImm(1); in selectIntrinsicWithSideEffects()
5063 MIB.buildInstr(AArch64::BRK, {}, {}) in selectIntrinsicWithSideEffects()
5179 MIB.buildInstr(AArch64::XPACLRI); in selectIntrinsic()
[all …]
H A DAArch64CallLowering.cpp405 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
427 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
904 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
1015 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0); in lowerTailCall()
1076 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
1149 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()
H A DAArch64LegalizerInfo.cpp911 auto ADRP = MIRBuilder.buildInstr(AArch64::ADRP, {LLT::pointer(0, 64)}, {}) in legalizeSmallCMGlobalValue()
932 ADRP = MIRBuilder.buildInstr(AArch64::MOVKXi, {LLT::pointer(0, 64)}, {ADRP}) in legalizeSmallCMGlobalValue()
939 MIRBuilder.buildInstr(AArch64::G_ADD_LOW, {DstReg}, {ADRP}) in legalizeSmallCMGlobalValue()
1209 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASDesired}, {}) in legalizeAtomicCmpxchg128()
1214 MIRBuilder.buildInstr(TargetOpcode::REG_SEQUENCE, {CASNew}, {}) in legalizeAtomicCmpxchg128()
1220 CAS = MIRBuilder.buildInstr(Opcode, {CASDst}, {CASDesired, CASNew, Addr}); in legalizeAtomicCmpxchg128()
1247 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
H A DAArch64PostLegalizerCombiner.cpp106 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
217 auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS}); in matchAArch64MulConstCombine()
H A DAArch64GlobalISelUtils.cpp90 .buildInstr(TargetOpcode::G_BZERO, {}, in tryEmitBZero()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp116 B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags()); in applySelectFCmpToFMinToFMaxLegacy()
193 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, in applyUCharToFloat()
196 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, in applyUCharToFloat()
246 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
H A DAMDGPUPreLegalizerCombiner.cpp135 B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16}, in applyClampI64ToI16()
145 auto Med3 = B.buildInstr( in applyClampI64ToI16()
H A DAMDGPURegisterBankInfo.cpp787 B.buildInstr(TargetOpcode::PHI) in executeInWaterfallLoop()
795 B.buildInstr(TargetOpcode::G_PHI) in executeInWaterfallLoop()
882 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
966 B.buildInstr(CmpOp) in executeInWaterfallLoop()
975 B.buildInstr(WaveAndOpc) in executeInWaterfallLoop()
1004 B.buildInstr(AndSaveExecOpc) in executeInWaterfallLoop()
1011 B.buildInstr(XorTermOpc) in executeInWaterfallLoop()
1029 B.buildInstr(MovTermOpc) in executeInWaterfallLoop()
1885 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1888 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
[all …]
H A DAMDGPUCallLowering.cpp314 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
351 B.buildInstr(AMDGPU::S_ENDPGM) in lowerReturn()
1124 CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP); in lowerTailCall()
1218 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0); in lowerTailCall()
1290 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP) in lowerCall()
1372 MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN) in lowerCall()
H A DAMDGPULegalizerInfo.cpp1796 B.buildInstr(AMDGPU::S_GETREG_B32) in getSegmentAperture()
3318 B.buildInstr(AMDGPU::S_DENORM_MODE) in toggleSPDenormMode()
3874 auto MIB = B.buildInstr(Opc) in legalizeBufferStore()
3975 auto MIB = B.buildInstr(Opc) in legalizeBufferLoad()
4016 B.buildInstr(Opc) in legalizeAtomicIncDec()
4715 B.buildInstr(AMDGPU::S_TRAP) in legalizeTrapHsaQueuePtr()
4725 B.buildInstr(AMDGPU::S_TRAP) in legalizeTrapHsa()
4744 B.buildInstr(AMDGPU::S_TRAP) in legalizeDebugTrapIntrinsic()
4860 B.buildInstr(AMDGPU::SI_IF) in legalizeIntrinsic()
4865 B.buildInstr(AMDGPU::SI_ELSE) in legalizeIntrinsic()
[all …]
H A DAMDGPURegBankCombiner.cpp137 B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)}, in applyMed3()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm()
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) in materialize32BitImm()
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
617 MachineInstrBuilder PairF64 = B.buildInstr( in select()
806 MachineInstrBuilder MIB = B.buildInstr( in select()
H A DMipsLegalizerInfo.cpp468 if (!MIRBuilder.buildInstr(Opcode) in SelectMSA3OpIntrinsic()
483 MIRBuilder.buildInstr(Opcode) in MSA3OpIntrinsicToGeneric()
495 MIRBuilder.buildInstr(Opcode) in MSA2OpIntrinsicToGeneric()
513 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); in legalizeIntrinsic()
H A DMipsCallLowering.cpp458 MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); in lowerCall()
560 MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0); in lowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp302 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown); in lowerCall()
344 MIRBuilder.buildInstr(X86::MOV8ri) in lowerCall()
390 MIRBuilder.buildInstr(AdjStackUp) in lowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp41 MIRBuilder.buildInstr(PPC::BLR8); in lowerReturn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp459 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); in lowerCall()
526 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP) in lowerCall()

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