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Searched refs:buildCopy (Results 1 – 22 of 22) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp174 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
175 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
219 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
232 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
274 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
275 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
416 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
523 MIRBuilder.buildCopy( in lowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
385 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp78 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
112 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
196 SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0); in getStackAddress()
209 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
377 B.buildCopy(ReturnAddrVReg, LiveInReturn); in lowerReturn()
473 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
599 B.buildCopy(LiveInReturn, ReturnAddrReg); in lowerFormalArguments()
1091 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1093 MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg); in handleImplicitCallArguments()
1098 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp846 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1094 Reg = B.buildCopy(Ty, Reg).getReg(0); in constrainOpWithReadfirstlane()
1279 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1407 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0); in setBufferOffsets()
1936 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
1985 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldExtractEltToCmpSelect()
2021 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
2086 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldInsertEltToCmpSelect()
2168 auto Copy = B.buildCopy(LLT::scalar(1), SrcReg); in applyMappingImpl()
2475 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
[all …]
H A DAMDGPULegalizerInfo.cpp2824 B.buildCopy(DstReg, LiveIn); in loadInputValue()
4714 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
288 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
295 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp251 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
276 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
450 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
496 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1139 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp971 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
1947 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp); in preISelLower()
2537 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3742 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
5131 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
5149 MIB.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
5180 MIB.buildCopy({DstReg}, {Register(AArch64::LR)}); in selectIntrinsic()
5198 MIB.buildCopy({DstReg}, {FrameAddr}); in selectIntrinsic()
5210 MIB.buildCopy({DstReg}, {Register(AArch64::LR)}); in selectIntrinsic()
5976 auto Copy = MIB.buildCopy({&RC}, {Reg}); in moveScalarRegClass()
[all …]
H A DAArch64PostLegalizerCombiner.cpp230 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp269 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
635 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
639 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp332 MIRBuilder.buildCopy( in translateCompare()
335 MIRBuilder.buildCopy( in translateCompare()
1285 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1329 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1440 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1556 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2100 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2114 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2144 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2592 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
H A DCSEMIRBuilder.cpp147 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp700 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1162 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1166 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DMachineIRBuilder.cpp238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
501 return buildCopy(Dst, Src); in buildCast()
H A DLegalizerHelper.cpp913 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); in narrowScalar()
5339 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
6715 MIRBuilder.buildCopy(DstReg, Val); in lowerShuffleVector()
6764 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
6779 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
6780 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
7181 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7183 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
H A DCombinerHelper.cpp130 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
336 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
683 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2349 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/GlSel/
H A DM68kCallLowering.cpp39 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h451 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
H A DSplitKit.cpp548 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, in buildCopy() function in SplitEditor
632 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h508 Builder.buildCopy(DstReg, SrcReg); in replaceRegOrBuildCopy()
H A DMachineIRBuilder.h809 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);