| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 771 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 772 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 780 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction() 781 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 782 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 790 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction() 791 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 792 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() 814 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction() 815 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF() 628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF() 642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6() 1095 MI.addOperand( in DecodeDEXT() 1097 MI.addOperand( in DecodeDEXT() 1138 MI.addOperand( in DecodeDINS() 1140 MI.addOperand( in DecodeDINS() 2586 MI.addOperand( in DecodeBgtzGroupBranchMMR6() 2590 MI.addOperand( in DecodeBgtzGroupBranchMMR6() 2631 MI.addOperand( in DecodeBlezGroupBranchMMR6() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2550 Inst.addOperand(MCOperand::createImm( in addRegShiftedRegOperands() 2561 Inst.addOperand(MCOperand::createImm( in addRegShiftedImmOperands() 5748 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply() 8682 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction() 8683 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() 8684 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() 8687 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction() 8688 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction() 8704 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction() 8705 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 216 CompoundInsn->addOperand(Rt); in getCompoundInsn() 228 CompoundInsn->addOperand(Rt); in getCompoundInsn() 229 CompoundInsn->addOperand(Rs); in getCompoundInsn() 242 CompoundInsn->addOperand(Rs); in getCompoundInsn() 243 CompoundInsn->addOperand(Rt); in getCompoundInsn() 255 CompoundInsn->addOperand(Rs); in getCompoundInsn() 256 CompoundInsn->addOperand(Rt); in getCompoundInsn() 268 CompoundInsn->addOperand(Rs); in getCompoundInsn() 269 CompoundInsn->addOperand(Rt); in getCompoundInsn() 286 CompoundInsn->addOperand(Rs); in getCompoundInsn() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset() 284 Inst.addOperand(Reg); in HexagonProcessInstruction() 286 Inst.addOperand(S16); in HexagonProcessInstruction() 337 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 353 TmpInst.addOperand(Reg); in HexagonProcessInstruction() 366 MappedInst.addOperand(Ps); in HexagonProcessInstruction() 444 TmpInst.addOperand( in HexagonProcessInstruction() 480 TmpInst.addOperand( in HexagonProcessInstruction() 507 TmpInst.addOperand( in HexagonProcessInstruction() 520 TmpInst.addOperand(Rdd); in HexagonProcessInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg() 38 Inst.addOperand(MCOperand::createImm(Val)); in addImm() 44 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm() 50 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm() 56 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr() 62 Inst.addOperand(MCOperand::createInst(Val)); in addInst() 67 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function 68 Inst.addOperand(Op); in addOperand()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget() 87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass() 203 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 219 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand() 263 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands() 284 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands() 300 Inst.addOperand(MCOperand::createImm(Disp)); in decodeMemRIHashOperands() 301 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands() 359 Inst.addOperand(MCOperand::createImm(Disp << 3)); in decodeSPE8Operands() 374 Inst.addOperand(MCOperand::createImm(Disp << 2)); in decodeSPE4Operands() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 87 SICInst.addOperand(RD); in emitSIC() 95 BSICInst.addOperand(R1); in emitBSIC() 96 BSICInst.addOperand(R2); in emitBSIC() 107 LEAInst.addOperand(RD); in emitLEAzzi() 111 LEAInst.addOperand(Imm); in emitLEAzzi() 131 LEAInst.addOperand(RD); in emitLEAzii() 134 LEAInst.addOperand(RS1); in emitLEAzii() 135 LEAInst.addOperand(Imm); in emitLEAzii() 156 Inst.addOperand(RD); in emitBinary() 157 Inst.addOperand(RS1); in emitBinary() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass() 174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 256 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand() 297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand() 318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand() 342 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len4Operand() 343 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len4Operand() 354 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len8Operand() 355 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len8Operand() 366 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDRAddr12Operand() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0)); in getNop() 40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop() 41 NopInst.addOperand(MCOperand::createReg(0)); in getNop() 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop() 45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop() 46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop() 47 NopInst.addOperand(MCOperand::createReg(0)); in getNop() 48 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass() 85 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass() 96 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass() 107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass() 118 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass() 129 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass() 160 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass() 171 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass() 191 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM2RegisterClass() 385 Inst.addOperand(Inst.getOperand(0)); in decodeRVCInstrRdRs1UImm() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 132 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm() 137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm() 142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm() 153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex() 198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); in addRegMask() 225 MI->addOperand(*MF, MO); in add() 231 MI->addOperand(*MF, MO); in add() 237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); in addMetadata() 253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); in addIntrinsicID() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust() 170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass() 179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue() 181 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue() 191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue() 193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue() 203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue() 205 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue() 223 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch() 230 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1502 Inst.addOperand(MCOperand::createImm(Op)); in DecodeSORegImmOperand() 2307 Inst.addOperand( in DecodeMemMultipleWritebackInstruction() 3421 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLD3DupInstruction() 3554 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEModImmInstruction() 3555 Inst.addOperand(MCOperand::createImm(0)); in DecodeMVEModImmInstruction() 3580 Inst.addOperand(MCOperand::createImm(Qd)); in DecodeMVEVADCInstruction() 5833 Inst.addOperand(MCOperand::createImm(0)); in DecodeNEONComplexLane64Instruction() 6120 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSCCLRM() 6378 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSTRVLDR_SYSREG() 6631 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEVCMP() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 307 MI.addOperand(Imm4Op); in getInstruction() 739 Inst.addOperand( in DecodeMatrixTile() 968 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMRSSystemRegister() 978 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMSRSystemRegister() 1001 Inst.addOperand(MCOperand::createImm(1)); in DecodeFMOVLaneInstruction() 1164 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction() 1166 Inst.addOperand(MCOperand::createImm(imm)); in DecodeMoveImmInstruction() 1764 Inst.addOperand(MCOperand::createImm(imm)); in DecodeLogicalImmInstruction() 1781 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmInstruction() 1819 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmTiedInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 549 NewInst.addOperand(I); in canonicalizeImmediates() 1239 TmpInst.addOperand(Rdd); in makeCombineInst() 1240 TmpInst.addOperand(MO1); in makeCombineInst() 1241 TmpInst.addOperand(MO2); in makeCombineInst() 1351 Inst.addOperand(Reg); in processInstruction() 1353 Inst.addOperand(S27); in processInstruction() 1639 TmpInst.addOperand(Rx); in processInstruction() 1640 TmpInst.addOperand(Rx); in processInstruction() 1641 TmpInst.addOperand(Rs); in processInstruction() 1659 TmpInst.addOperand(Rx); in processInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 132 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass() 186 Inst.addOperand(MCOperand::createImm(Offset)); in DecodeSymbolicOperandOff() 204 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand() 216 Inst.addOperand( in DecodeFromCyclicRange() 233 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction() 234 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction() 251 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction() 252 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction() 286 Inst.addOperand(MCOperand::createImm(Value)); in DecodeMoveHRegInstruction() 308 Inst.addOperand(MCOperand::createImm(U6Field)); in DecodeCCRU6Instruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR() 182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX() 183 TmpInst.addOperand(Op1); in emitRX() 202 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII() 203 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII() 213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX() 214 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX() 215 TmpInst.addOperand(Op2); in emitRRX() 231 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX() 232 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 1088 MI.addOperand(Dest); in LowerFAULTING_OP() 1109 MOVI.addOperand(MCOperand::createImm(0)); in emitFMov0() 1193 MovZ.addOperand(Hi_MCSym); in emitInstruction() 1201 MovK.addOperand(Lo_MCSym); in emitInstruction() 1202 MovK.addOperand(MCOperand::createImm(0)); in emitInstruction() 1261 TmpInst.addOperand(Dest); in emitInstruction() 1304 Adrp.addOperand(SymTLSDesc); in emitInstruction() 1316 Ldr.addOperand(SymTLSDescLo12); in emitInstruction() 1317 Ldr.addOperand(MCOperand::createImm(0)); in emitInstruction() 1330 Add.addOperand(SymTLSDescLo12); in emitInstruction() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 515 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr() 520 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands() 528 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands() 537 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands() 571 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands() 580 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands() 583 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands() 592 Inst.addOperand(MCOperand::createExpr(getMemDisp())); in addAbsMemOperands() 597 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands() 598 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 152 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass() 163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass() 175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass() 187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass() 202 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass() 213 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass() 407 MI.addOperand(MCOperand::createImm(asi)); in DecodeMem() 516 MI.addOperand(MCOperand::createImm(tgt)); in DecodeCall() 523 MI.addOperand(MCOperand::createImm(tgt)); in DecodeSIMM13() 624 MI.addOperand(MCOperand::createImm(asi)); in DecodeSWAP() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 817 Inst.addOperand(MCOperand::createImm(Imm)); in addExpr() 819 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr() 825 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands() 857 Inst.addOperand(MCOperand::createImm(Imm)); in addFenceArgOperands() 867 Inst.addOperand(MCOperand::createImm(getVType())); in addVTypeIOperands() 2259 .addOperand(DestReg) in emitAuipcInstPair() 2260 .addOperand(TmpReg) in emitAuipcInstPair() 2370 .addOperand(DestReg) in emitPseudoExtend() 2371 .addOperand(SourceReg) in emitPseudoExtend() 2375 .addOperand(DestReg) in emitPseudoExtend() [all …]
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/Disassembler/ |
| H A D | WebAssemblyDisassembler.cpp | 104 MI.addOperand(MCOperand::createImm(Val)); in parseLEBImmediate() 116 MI.addOperand( in parseImmediate() 119 MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val))); in parseImmediate() 228 MI.addOperand( in getInstruction() 231 MI.addOperand(MCOperand::createImm(Val & 0x7f)); in getInstruction() 240 MI.addOperand(MCOperand::createExpr(Expr)); in getInstruction() 259 MI.addOperand(MCOperand::createImm(Val & 0x7f)); in getInstruction() 261 MI.addOperand( in getInstruction()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMCInstLower.cpp | 196 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst() 202 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst() 217 OutMI.addOperand(MCOp); in lowerRISCVMachineInstrToMCInst() 236 OutMI.addOperand(MCOperand::createImm( in lowerRISCVMachineInstrToMCInst() 238 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst() 242 OutMI.addOperand( in lowerRISCVMachineInstrToMCInst() 244 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 133 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI32RegisterClass() 143 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegisterClass() 153 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeF32RegisterClass() 163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeF128RegisterClass() 177 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeV64RegisterClass() 187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVMRegisterClass() 197 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVM512RegisterClass() 322 MI.addOperand(MCOperand::createImm(0)); in DecodeASX() 353 MI.addOperand(MCOperand::createImm(0)); in DecodeAS() 522 MI.addOperand(MCOperand::createImm(tgt)); in DecodeSIMM7() [all …]
|