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Searched refs:ZeroReg (Results 1 – 22 of 22) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp802 ZeroReg = InProlog ? X86::RCX in emitStackProbeInlineWindowsCoreCLR64() local
862 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
863 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
864 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
871 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3169 Register ZeroReg, RegisterOperand GPROpnd> {
3177 (Addiu ZeroReg, tglobaladdr:$in)>;
3179 (Addiu ZeroReg, tblockaddress:$in)>;
3181 (Addiu ZeroReg, tjumptable:$in)>;
3183 (Addiu ZeroReg, tconstpool:$in)>;
3185 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3187 (Addiu ZeroReg, texternalsym:$in)>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1473 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1476 .addReg(ZeroReg).addImm(1) in SelectCmp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3276 MIB.addReg(ZeroReg); in copyGPRRegTuple()
5316 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5323 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5339 .addReg(ZeroReg) in genAlternativeCodeSequence()
5355 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
5359 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5365 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5373 .addReg(ZeroReg) in genAlternativeCodeSequence()
5408 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5415 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64ExpandPseudoInsts.cpp76 unsigned ExtendImm, unsigned ZeroReg,
186 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64InstrInfo.h162 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64FastISel.cpp380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
383 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4850 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4853 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
H A DAArch64ISelDAGToDAG.cpp2839 unsigned ZeroReg; in tryShiftAmountMod() local
2843 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2847 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2850 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64ISelLowering.cpp14849 unsigned ZeroReg; in replaceZeroVectorStore() local
14852 ZeroReg = AArch64::WZR; in replaceZeroVectorStore()
14855 ZeroReg = AArch64::XZR; in replaceZeroVectorStore()
14859 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); in replaceZeroVectorStore()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h872 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
876 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
882 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2741 SrcReg = ZeroReg; in loadImmediate()
4189 unsigned ZeroReg; in expandDivRem() local
4194 ZeroReg = Mips::ZERO_64; in expandDivRem()
4198 ZeroReg = Mips::ZERO; in expandDivRem()
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4229 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4235 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4254 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4274 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4302 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2218 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
2220 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
2221 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
2222 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2109 MCRegister ZeroReg; in onlyFoldImmediate() local
2112 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2114 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2118 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp11235 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
11302 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
11347 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
11391 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12282 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
12315 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
12372 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12396 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12409 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp4379 const Register ZeroReg = AArch64::WZR; in emitCSetForFCmp() local
4382 MIRBuilder.buildInstr(AArch64::CSINCWr, {CsetDst}, {ZeroReg, ZeroReg}) in emitCSetForFCmp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7293 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
7295 ZeroReg, 0); in convertNonUniformLoopRegion()
7296 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()