Lines Matching refs:ZeroReg
3261 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
3276 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4565 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4584 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4594 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4595 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4655 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
4657 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
5311 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5316 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5323 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5339 .addReg(ZeroReg) in genAlternativeCodeSequence()
5355 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
5359 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5365 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5373 .addReg(ZeroReg) in genAlternativeCodeSequence()
5403 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5408 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
5415 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
5430 .addReg(ZeroReg) in genAlternativeCodeSequence()