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Searched refs:VecVT (Results 1 – 25 of 28) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1191 VecVT = VecVT.getHalfNumVectorElementsVT(); in decomposeSubvectorInsertExtractToSubRegs()
1358 return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget); in getDefaultScalableVLOps()
3303 MVT ContainerVT = VecVT; in lowerVectorMaskTrunc()
3354 MVT ContainerVT = VecVT; in lowerINSERT_VECTOR_ELT()
3930 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
4010 MVT InterSubVT = VecVT; in lowerINSERT_SUBVECTOR()
4013 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
4078 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerEXTRACT_SUBVECTOR()
4146 MVT InterSubVT = VecVT; in lowerEXTRACT_SUBVECTOR()
4147 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerEXTRACT_SUBVECTOR()
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H A DRISCVISelLowering.h495 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp373 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
374 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
379 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
400 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
411 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
412 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
419 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
442 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp1279 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1521 return DAG.getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp_StrictFP()
1594 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
1595 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
1596 if (VecVT.getScalarSizeInBits() < 8) { in SplitVecRes_INSERT_VECTOR_ELT()
1628 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT); in SplitVecRes_INSERT_VECTOR_ELT()
2297 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE() local
2319 EVT VecVT = VecOp.getValueType(); in SplitVecOp_VECREDUCE_SEQ() local
2438 EVT VecVT = Vec.getValueType(); in SplitVecOp_EXTRACT_VECTOR_ELT() local
2462 EVT EltVT = VecVT.getVectorElementType(); in SplitVecOp_EXTRACT_VECTOR_ELT()
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H A DLegalizeDAG.cpp1364 EVT VecVT = Vec.getValueType(); in ExpandExtractFromVectorThroughStack() local
1368 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1376 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, in ExpandExtractFromVectorThroughStack()
1381 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandExtractFromVectorThroughStack()
1384 VecVT.getVectorElementType()); in ExpandExtractFromVectorThroughStack()
1409 EVT VecVT = Vec.getValueType(); in ExpandInsertToVectorThroughStack() local
1411 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandInsertToVectorThroughStack()
1421 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in ExpandInsertToVectorThroughStack()
H A DTargetLowering.cpp815 EVT VecVT = Vec.getValueType(); in SimplifyMultipleUseDemandedBits() local
816 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && in SimplifyMultipleUseDemandedBits()
1000 EVT VecVT = Vec.getValueType(); in SimplifyDemandedBits() local
1005 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { in SimplifyDemandedBits()
7805 EVT VecVT, const SDLoc &dl, in clampDynamicVectorIndex() argument
7807 if (!VecVT.isScalableVector() && isa<ConstantSDNode>(Idx)) in clampDynamicVectorIndex()
7811 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
7812 if (VecVT.isScalableVector()) { in clampDynamicVectorIndex()
7840 DAG, VecPtr, VecVT, in getVectorElementPointer()
7853 EVT EltVT = VecVT.getVectorElementType(); in getVectorSubVecPointer()
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H A DDAGCombiner.cpp18706 EVT VecVT = VecOp.getValueType(); in visitEXTRACT_VECTOR_ELT() local
18740 if (IndexC && VecVT.isFixedLengthVector() && in visitEXTRACT_VECTOR_ELT()
18747 TLI.isTypeLegal(VecVT) && in visitEXTRACT_VECTOR_ELT()
18750 VecVT.isFixedLengthVector()) && in visitEXTRACT_VECTOR_ELT()
18765 if (VecVT.isScalableVector()) in visitEXTRACT_VECTOR_ELT()
18771 unsigned NumElts = VecVT.getVectorNumElements(); in visitEXTRACT_VECTOR_ELT()
18893 EVT ExtVT = VecVT.getVectorElementType(); in visitEXTRACT_VECTOR_ELT()
19114 if (!isTypeLegal(VecVT) || in reduceBuildVecExtToExtBuildVec()
19120 SDValue BV = DAG.getBuildVector(VecVT, DL, Ops); in reduceBuildVecExtToExtBuildVec()
20188 EVT VecVT = BinOp.getValueType(); in narrowInsertExtractVectorBinOp() local
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H A DSelectionDAG.cpp3404 EVT VecVT = InVec.getValueType(); in computeKnownBits() local
3406 if (VecVT.isScalableVector()) in computeKnownBits()
3408 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); in computeKnownBits()
3409 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in computeKnownBits()
4067 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits() local
4069 if (VecVT.isScalableVector()) in ComputeNumSignBits()
4073 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in ComputeNumSignBits()
10068 EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE); in UnrollVectorOp() local
10069 return getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp()
H A DLegalizeFloatTypes.cpp2338 EVT VecVT = Vec->getValueType(0); in PromoteFloatRes_EXTRACT_VECTOR_ELT() local
2339 EVT EltVT = VecVT.getVectorElementType(); in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2343 switch (getTypeAction(VecVT)) { in PromoteFloatRes_EXTRACT_VECTOR_ELT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4178 if (VecVT.isFloatingPoint()) { in getVCmpInst()
4201 if (VecVT == MVT::v4f32) in getVCmpInst()
4203 else if (VecVT == MVT::v2f64) in getVCmpInst()
4208 if (VecVT == MVT::v4f32) in getVCmpInst()
4210 else if (VecVT == MVT::v2f64) in getVCmpInst()
4215 if (VecVT == MVT::v4f32) in getVCmpInst()
4217 else if (VecVT == MVT::v2f64) in getVCmpInst()
4245 if (VecVT == MVT::v16i8) in getVCmpInst()
4257 if (VecVT == MVT::v16i8) in getVCmpInst()
4269 if (VecVT == MVT::v16i8) in getVCmpInst()
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H A DPPCISelLowering.cpp8355 EVT VecVT = Vec.getValueType(); in widenVec() local
8356 assert(VecVT.isVector() && "Expected a vector type."); in widenVec()
8357 assert(VecVT.getSizeInBits() < 128 && "Vector is already full width."); in widenVec()
8359 EVT EltVT = VecVT.getVectorElementType(); in widenVec()
8363 unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements(); in widenVec()
8366 SDValue UndefVec = DAG.getUNDEF(VecVT); in widenVec()
8960 EVT VecVT = V->getValueType(0); in haveEfficientBuildVectorPattern() local
8961 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
8962 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
8963 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5298 EVT VecVT = Op0.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5845 if (Op.getValueType() != VecVT) { in combineExtract()
5865 EVT VecVT = Vec.getValueType(); in combineTruncateExtract() local
5866 if (canTreatAsByteVector(VecVT)) { in combineTruncateExtract()
6187 EVT VecVT = Op.getValueType(); in combineEXTRACT_VECTOR_ELT() local
6203 EVT VecVT = Op0.getValueType(); in combineEXTRACT_VECTOR_ELT() local
6452 EVT VecVT = N->getValueType(0); in combineBSWAP() local
6454 if (VecVT != Vec.getValueType()) { in combineBSWAP()
6481 EVT VecVT = N->getValueType(0); in combineBSWAP() local
6482 if (VecVT != Op0.getValueType()) { in combineBSWAP()
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H A DSystemZISelLowering.h664 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
751 MVT VecVT; member
H A DSystemZISelDAGToDAG.cpp1156 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); in loadVectorConstant()
1162 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1164 if (VCI.VecVT == VT.getSimpleVT()) in loadVectorConstant()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3559 VecVT = MVT::v8f32; in forwardMustTailParameters()
3561 VecVT = MVT::v4f32; in forwardMustTailParameters()
18828 if (VecVT.is256BitVector() || VecVT.is512BitVector()) { in LowerEXTRACT_VECTOR_ELT()
18899 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
18915 Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask); in LowerEXTRACT_VECTOR_ELT()
40901 if ((VecVT.is256BitVector() || VecVT.is512BitVector()) && in combineExtractWithShuffle()
40912 if ((VecVT == MVT::v4i32 || VecVT == MVT::v2i64) && in combineExtractWithShuffle()
41131 SDValue Lo = getUnpackl(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
41132 SDValue Hi = getUnpackh(DAG, DL, VecVT, Rdx, DAG.getUNDEF(VecVT)); in combineArithReduction()
41164 if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) { in combineArithReduction()
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H A DX86ISelDAGToDAG.cpp424 MVT VecVT = N->getOperand(0).getSimpleValueType(); in getExtractVEXTRACTImmediate() local
425 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getExtractVEXTRACTImmediate()
432 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
433 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getInsertVINSERTImmediate()
1124 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 : MVT::v4f32; in PreprocessISelDAG() local
1126 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1128 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1133 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG()
1145 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); in PreprocessISelDAG()
1147 Res = CurDAG->getNode(N->getOpcode(), dl, VecVT, Op0, Op1); in PreprocessISelDAG()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5443 EVT VecVT = Vec.getValueType(); in lowerINSERT_SUBVECTOR() local
5445 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_SUBVECTOR()
5464 EVT VecVT = Vec.getValueType(); in lowerINSERT_VECTOR_ELT() local
5465 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT()
5466 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT()
5542 EVT VecVT = Vec.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5543 unsigned VecSize = VecVT.getSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
7562 EVT VecVT = in handleD16VData() local
10097 EVT VecVT = Vec.getValueType(); in shouldExpandVectorDynExt() local
10111 EVT VecVT = Vec.getValueType(); in performExtractVectorEltCombine() local
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H A DAMDGPUISelLowering.h188 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
H A DR600ISelLowering.cpp675 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
676 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
679 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { in vectorToVerticalVector()
684 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6078 EVT VecVT = EVT::getVectorVT( in CombineVMOVDRRCandidateWithVecOp() local
8723 EVT VecVT = Op.getOperand(0).getValueType(); in LowerINSERT_VECTOR_ELT_i1() local
8770 EVT VecVT = VecIn.getValueType(); in LowerINSERT_VECTOR_ELT() local
12925 if (!VecVT.isPow2VectorType() || VecVT.getVectorNumElements() == 1) in PerformVQDMULHCombine()
12928 VecVT.getScalarType() != ScalarType || in PerformVQDMULHCombine()
12937 if (VecVT.getSizeInBits() < 128) { in PerformVQDMULHCombine()
14559 if (!TLI.isTypeLegal(VecVT)) in PerformARMBUILD_VECTORCombine()
14567 SDValue Vec = DAG.getUNDEF(VecVT); in PerformARMBUILD_VECTORCombine()
14734 EVT VecVT = Op0.getValueType(); in PerformExtractEltToVMOVRRD() local
14736 if (VecVT.getVectorNumElements() != 4) in PerformExtractEltToVMOVRRD()
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H A DARMISelDAGToDAG.cpp4314 EVT VecVT = N->getValueType(0); in Select() local
4315 EVT EltVT = VecVT.getVectorElementType(); in Select()
4316 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
4320 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4326 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4331 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2811 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { in aggressivelyPreferBuildVectorSources() argument
4507 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4515 SDValue getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp368 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
369 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
374 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp89 for (MVT VecVT : AllVectorVTs) in initRegisterClasses() local
90 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7005 EVT VecVT; in LowerFCOPYSIGN() local
7011 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
7012 DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
7013 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
7016 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); in LowerFCOPYSIGN()
7017 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); in LowerFCOPYSIGN()
7022 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32); in LowerFCOPYSIGN()
7026 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
7035 VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16); in LowerFCOPYSIGN()
7042 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT); in LowerFCOPYSIGN()
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