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Searched refs:VecReg (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp679 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair() argument
680 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
681 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
684 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair() argument
685 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
688 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle() argument
689 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); in IsVecRegSingle()
H A DHexagonMCInstrInfo.h354 bool IsVecRegSingle(unsigned VecReg);
355 bool IsVecRegPair(unsigned VecReg);
356 bool IsReverseVecRegPair(unsigned VecReg);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp264 Register VecReg, unsigned LaneIdx,
3346 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
3347 LLT VecTy = MRI.getType(VecReg); in selectReduction()
3354 {VecReg, VecReg}); in selectReduction()
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
3889 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
3890 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
3899 Register InsertReg = VecReg; in emitExtractVectorElt()
3905 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
3915 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1854 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1857 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
1861 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1863 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1882 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1895 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1897 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1898 .addReg(VecReg, in expandPostRAPseudo()
1922 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1934 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
[all …]
H A DAMDGPURegisterBankInfo.cpp1953 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1961 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1997 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
2051 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
2059 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2100 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
H A DAMDGPUInstructionSelector.cpp2732 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
2741 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2757 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2783 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
2793 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp3679 unsigned VecReg, in computeIndirectRegAndOffset() argument
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2424 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2425 LLT VecTy = MRI.getType(VecReg); in widenScalar()
2449 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2450 LLT VecTy = MRI.getType(VecReg); in widenScalar()