1854     Register VecReg = MI.getOperand(0).getReg();  in expandPostRAPseudo()  local
1857     assert(VecReg == MI.getOperand(1).getReg());  in expandPostRAPseudo()
1861         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
1863         .addReg(VecReg, RegState::ImplicitDefine)  in expandPostRAPseudo()
1864         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0));  in expandPostRAPseudo()
1882     Register VecReg = MI.getOperand(0).getReg();  in expandPostRAPseudo()  local
1895             .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
1897             .addReg(VecReg, RegState::ImplicitDefine)  in expandPostRAPseudo()
1898             .addReg(VecReg,  in expandPostRAPseudo()
1922     Register VecReg = MI.getOperand(1).getReg();  in expandPostRAPseudo()  local
1934         .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)  in expandPostRAPseudo()
1935         .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0))  in expandPostRAPseudo()