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Searched refs:ValueReg (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h50 unsigned ValueReg, unsigned Address,
56 unsigned ValueReg, unsigned Address,
246 unsigned ValueReg, unsigned Address,
254 unsigned ValueReg, unsigned Address,
H A DSIRegisterInfo.cpp953 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
954 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1163 ? ValueReg in buildSpillLoadStore()
1164 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1186 : ValueReg; in buildSpillLoadStore()
1191 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1199 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1215 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1237 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1268 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
[all …]
H A DR600InstrInfo.cpp1093 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1095 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1100 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1116 AddrReg, ValueReg) in buildIndirectWrite()
1125 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1127 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1132 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1148 ValueReg, in buildIndirectRead()
H A DSIRegisterInfo.h354 int Index, Register ValueReg, bool ValueIsKill,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1287 unsigned ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1288 if (ValueReg == 0) in selectStore()
1291 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1297 MIB.addReg(ValueReg); in selectStore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
191 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
221 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11219 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
11220 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
11222 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
11364 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
11367 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11368 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
11373 .addReg(ValueReg); in EmitPartwordAtomicBinary()
11374 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
11379 .addReg(ValueReg); in EmitPartwordAtomicBinary()