Lines Matching refs:ValueReg
939 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
953 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
954 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1041 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1059 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1163 ? ValueReg in buildSpillLoadStore()
1164 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1185 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1186 : ValueReg; in buildSpillLoadStore()
1191 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1199 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1215 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1237 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1268 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1278 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); in buildSpillLoadStore()