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Searched refs:VTList (Results 1 – 15 of 15) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h976 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
982 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1005 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
1006 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
1130 SDVTList VTList, ArrayRef<SDValue> Ops,
1138 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1145 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
1151 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1474 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
1476 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList,
[all …]
H A DTargetRegisterInfo.h237 vt_iterator VTList; member
314 return getRegClassInfo(RC).VTList; in legalclasstypes_begin()
H A DSelectionDAGISel.h325 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp2628 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); in ExpandIntRes_ADDSUB() local
2630 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2632 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2634 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
2636 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2649 SDVTList VTList = DAG.getVTList(NVT, OvfVT); in ExpandIntRes_ADDSUB() local
2727 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
2729 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
2731 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
2733 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
[all …]
H A DSelectionDAG.cpp563 ID.AddPointer(VTList.VTs); in AddNodeIDValueTypes()
587 AddNodeIDValueTypes(ID, VTList); in AddNodeIDNode()
7124 AddNodeIDNode(ID, Opcode, VTList, Ops); in getAtomic()
7232 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getMemIntrinsicNode()
8023 if (VTList.NumVTs == 1) in getNode()
8041 assert((!VTList.VTs[0].isVector() || in getNode()
8053 assert((!VTList.VTs[0].isVector() || in getNode()
8089 if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { in getNode()
8119 return getNode(Opcode, DL, VTList, Ops); in getNode()
8734 if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) { in getNodeIfExists()
[all …]
H A DSelectionDAGISel.cpp2480 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, in MorphNode() argument
2501 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); in MorphNode()
3501 SDVTList VTList; in SelectCodeCommon() local
3503 VTList = CurDAG->getVTList(VTs[0]); in SelectCodeCommon()
3505 VTList = CurDAG->getVTList(VTs[0], VTs[1]); in SelectCodeCommon()
3507 VTList = CurDAG->getVTList(VTs); in SelectCodeCommon()
3563 VTList, Ops); in SelectCodeCommon()
3582 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList, in SelectCodeCommon()
H A DScheduleDAGSDNodes.cpp146 SDVTList VTList = DAG->getVTList(VTs); in CloneNodeWithValues() local
154 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); in CloneNodeWithValues()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp489 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
505 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdHi), VTList, in matchLoadD16FromBuildVector()
523 SDVTList VTList = CurDAG->getVTList(VT, MVT::Other); in matchLoadD16FromBuildVector() local
539 CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdLo), VTList, in matchLoadD16FromBuildVector()
1101 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue); in SelectADD_SUB_I64() local
1115 AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args); in SelectADD_SUB_I64()
1118 AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args); in SelectADD_SUB_I64()
1125 SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs); in SelectADD_SUB_I64()
H A DSIISelLowering.h115 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
H A DSIISelLowering.cpp4700 VTList, Ops, M->getMemoryVT(), in adjustLoadValueType()
4735 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad() local
6414 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue}); in lowerSBuffer() local
7482 EVT VT = VTList.VTs[0]; in getMemIntrinsicNode()
7494 assert(VTList.NumVTs == 2); in getMemIntrinsicNode()
8359 return DAG.getNode(Opcode, SL, VTList, in getFPBinOp()
8381 return DAG.getNode(Opcode, SL, VTList, in getFPTernOp()
10386 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); in performAddCombine() local
10389 return DAG.getNode(Opc, SL, VTList, Args); in performAddCombine()
10427 SDVTList VTList = DAG.getVTList(MVT::i32, MVT::i1); in performSubCombine() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2631 SDVTList VTList = DAG.getVTList(VT, VT); in lowerShiftRightParts() local
2634 DL, VTList, Cond, ShiftRightHi, in lowerShiftRightParts()
2653 SDVTList VTList = DAG.getVTList(VT, MVT::Other); in createLoadLR() local
2660 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createLoadLR()
2734 SDVTList VTList = DAG.getVTList(MVT::Other); in createStoreLR() local
2741 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createStoreLR()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h200 TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
H A DCodeGenDAGPatterns.cpp69 TypeSetByHwMode::TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList) { in TypeSetByHwMode() argument
70 for (const ValueTypeByHwMode &VVT : VTList) { in TypeSetByHwMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3998 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() local
4001 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, in lowerATOMIC_LOAD_OP()
4101 SDVTList VTList = DAG.getVTList(WideVT, MVT::i32, MVT::Other); in lowerATOMIC_CMP_SWAP() local
4105 VTList, Ops, NarrowVT, MMO); in lowerATOMIC_CMP_SWAP()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5580 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond() local
5582 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops); in OptimizeVFPBrcond()
5697 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC() local
5699 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
5703 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
19684 SDVTList VTList = DAG.getVTList(HalfT, MVT::i1); in lowerABS() local
19694 Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo); in lowerABS()
19695 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi, in lowerABS()