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Searched refs:VGPR (Results 1 – 17 of 17) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td143 (sequence "VGPR%u", 24, 255)
147 (sequence "VGPR%u", 32, 255)
153 (sequence "VGPR%u", 56, 63),
154 (sequence "VGPR%u", 72, 79),
155 (sequence "VGPR%u", 88, 95),
156 (sequence "VGPR%u", 104, 111),
157 (sequence "VGPR%u", 120, 127),
158 (sequence "VGPR%u", 136, 143),
159 (sequence "VGPR%u", 152, 159),
160 (sequence "VGPR%u", 168, 175),
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H A DSIRegisterInfo.td284 // VGPR registers
286 defm VGPR#Index :
507 // VGPR 32-bit registers
516 // VGPR 64-bit registers
519 // VGPR 96-bit registers
522 // VGPR 128-bit registers
525 // VGPR 160-bit registers
528 // VGPR 192-bit registers
531 // VGPR 224-bit registers
534 // VGPR 256-bit registers
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H A DSIFrameLowering.cpp85 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
106 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
779 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitPrologue()
785 auto VGPR = Reg.first; in emitPrologue() local
853 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) in emitPrologue()
856 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
873 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
1042 .addReg(Spill[0].VGPR) in emitEpilogue()
1068 .addReg(Spill[0].VGPR) in emitEpilogue()
1088 auto VGPR = Reg.first; in emitEpilogue() local
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H A DSIMachineFunctionInfo.h442 Register VGPR;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
449 bool hasReg() { return VGPR != 0;}
454 Register VGPR;
460 SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
526 SpillVGPRs[Index].VGPR = NewVGPR;
H A DAMDGPURegisterBanks.td13 def VGPRRegBank : RegisterBank<"VGPR",
H A DSILowerSGPRSpills.cpp269 return SpillRegInfo.VGPR == PreReservedVGPR; in lowerShiftReservedVGPR()
361 MBB.addLiveIn(SSpill.VGPR); in runOnMachineFunction()
H A DSIMachineFunctionInfo.cpp324 assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR); in allocateSGPRSpillToVGPR()
357 LaneVGPR = SpillVGPRs.back().VGPR; in allocateSGPRSpillToVGPR()
640 if (i->VGPR == ReservedVGPR) { in removeVGPRForSGPRSpill()
H A DSIInstrInfo.td80 SDTCisVT<2, i32>, // vindex(VGPR)
81 SDTCisVT<3, i32>, // voffset(VGPR)
98 SDTCisVT<2, i32>, // vindex(VGPR)
99 SDTCisVT<3, i32>, // voffset(VGPR)
116 SDTCisVT<2, i32>, // vindex(VGPR)
117 SDTCisVT<3, i32>, // voffset(VGPR)
142 SDTCisVT<2, i32>, // vindex(VGPR)
143 SDTCisVT<3, i32>, // voffset(VGPR)
199 SDTCisVT<4, i32>, // vindex(VGPR)
200 SDTCisVT<5, i32>, // voffset(VGPR)
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H A DAMDGPUGenRegisterBankInfo.def58 {0, 1, VGPRRegBank}, // VGPR begin
H A DSIPeepholeSDWA.cpp1182 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in legalizeScalarOperands() local
1184 TII->get(AMDGPU::V_MOV_B32_e32), VGPR); in legalizeScalarOperands()
1190 Op.ChangeToRegister(VGPR, false); in legalizeScalarOperands()
H A DSIRegisterInfo.cpp582 reserveRegisterTuples(Reserved, SpilledVGPR.VGPR); in getReservedRegs()
594 reserveRegisterTuples(Reserved, SSpill.VGPR); in getReservedRegs()
1351 Spill.VGPR) in spillSGPR()
1354 .addReg(Spill.VGPR); in spillSGPR()
1461 .addReg(Spill.VGPR) in restoreSGPR()
H A DSISchedule.td242 // Add 1 stall cycle for VGPR read.
H A DVOP1Instructions.td306 // Restrict src0 to be VGPR
863 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
H A DAMDGPU.td250 …"Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of…
362 "Has VGPR mode register indexing"
H A DSIInstructions.td638 // These variants of V_INDIRECT_REG_READ/WRITE use VGPR indexing. By using these
640 // that switch the VGPR indexing mode. Spills to accvgprs could be effected by
709 // VGPR or AGPR spill instructions. In case of AGPR spilling a temp register
710 // needs to be used and an extra instruction to move between VGPR and AGPR.
2481 // Avoid pointlessly materializing a constant in VGPR.
H A DVOP3Instructions.td596 // blocking folding SGPR->VGPR copies later.
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td925 [data_ty, // vdata(VGPR)
975 [data_ty, // vdata(VGPR)
990 [data_ty, // vdata(VGPR)
1027 [LLVMMatchType<0>, // src(VGPR)
1028 LLVMMatchType<0>, // cmp(VGPR)
1067 [LLVMMatchType<0>, // src(VGPR)
1068 LLVMMatchType<0>, // cmp(VGPR)
1106 llvm_i32_ty, // vindex(VGPR)
1204 [llvm_i32_ty, // src(VGPR)
1205 llvm_i32_ty, // cmp(VGPR)
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