Lines Matching refs:VGPR
85 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
106 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
779 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitPrologue()
785 auto VGPR = Reg.first; in emitPrologue() local
794 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitPrologue()
853 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) in emitPrologue()
856 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
870 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) in emitPrologue()
873 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
1042 .addReg(Spill[0].VGPR) in emitEpilogue()
1068 .addReg(Spill[0].VGPR) in emitEpilogue()
1083 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR, in emitEpilogue()
1088 auto VGPR = Reg.first; in emitEpilogue() local
1097 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI); in emitEpilogue()
1261 SavedVGPRs.reset(SSpill.VGPR); in determineCalleeSaves()