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Searched refs:VECTOR_REG_CAST (Results 1 – 3 of 3) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1682 MAKE_CASE(ARMISD::VECTOR_REG_CAST) in getTargetNodeName()
7707 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
8102 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
12945 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
12946 Inp1 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp1); in PerformVQDMULHCombine()
14315 BV.getOpcode() == ARMISD::VECTOR_REG_CAST) && in PerformVMOVRRDCombine()
14640 if (Op->getOpcode() == ARMISD::VECTOR_REG_CAST) { in PerformVECTOR_REG_CASTCombine()
14762 DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0), in PerformExtractEltToVMOVRRD()
17361 while (Src.getOpcode() == ARMISD::VECTOR_REG_CAST) in PerformBITCASTCombine()
17563 SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V); in PerformMVEExtCombine()
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H A DARMISelLowering.h140 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register enumerator
H A DARMInstrInfo.td310 // 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a
313 // the _memory_ storage format of the vector, whereas VECTOR_REG_CAST
317 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
322 // VECTOR_REG_CAST emits no code at all if the vector is already in a register.
323 def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>;
325 // In little-endian, VECTOR_REG_CAST is often turned into bitconvert during
327 // that needs to match something that's _logically_ a VECTOR_REG_CAST must
331 // matches VECTOR_REG_CAST in either endianness, and also bitconvert in the