1682     MAKE_CASE(ARMISD::VECTOR_REG_CAST)  in getTargetNodeName()
4121     return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),  in LowerINTRINSIC_WO_CHAIN()
7707         return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup);  in LowerBUILD_VECTOR()
8050     Src.ShuffleVec = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, ShuffleVT, Src.ShuffleVec);  in ReconstructShuffle()
8102   return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle);  in ReconstructShuffle()
9916                              PassThru.getOpcode() == ARMISD::VECTOR_REG_CAST) &&  in LowerMLOAD()
12945     Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0);  in PerformVQDMULHCombine()
12946     Inp1 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp1);  in PerformVQDMULHCombine()
12948     SDValue Trunc = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, ExtVecVT, VQDMULH);  in PerformVQDMULHCombine()
13487       SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);  in PerformMVEVMULLCombine()
13488       SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1);  in PerformMVEVMULLCombine()
13494       SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);  in PerformMVEVMULLCombine()
13495       SDValue New1a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op1);  in PerformMVEVMULLCombine()
14315          BV.getOpcode() == ARMISD::VECTOR_REG_CAST) &&  in PerformVMOVRRDCombine()
14640   if (Op->getOpcode() == ARMISD::VECTOR_REG_CAST) {  in PerformVECTOR_REG_CASTCombine()
14644     return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Op->getOperand(0));  in PerformVECTOR_REG_CASTCombine()
14762       DCI.DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v2f64, Op0),  in PerformExtractEltToVMOVRRD()
14899         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)),  in PerformShuffleVMOVNCombine()
14900         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),  in PerformShuffleVMOVNCombine()
14905         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(1)),  in PerformShuffleVMOVNCombine()
14906         DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, Trunc.getOperand(0)),  in PerformShuffleVMOVNCombine()
15684     Extract = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v4i32, FPTrunc);  in PerformSplittingToNarrowingStores()
16688           DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, MVT::v8f16, Loads[i]);  in PerformSplittingToWideningLoad()
16811     SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN);  in PerformMinMaxCombine()
16852     SDValue Bitcast = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, VQMOVN);  in PerformMinMaxCombine()
17361   while (Src.getOpcode() == ARMISD::VECTOR_REG_CAST)  in PerformBITCASTCombine()
17372     return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(N), DstVT, Src);  in PerformBITCASTCombine()
17418             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)),  in PerformMVETruncCombine()
17419             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),  in PerformMVETruncCombine()
17424             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(1)),  in PerformMVETruncCombine()
17425             DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, S0->getOperand(0)),  in PerformMVETruncCombine()
17563     SDValue VVT = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, VT, V);  in PerformMVEExtCombine()
17727   case ARMISD::VECTOR_REG_CAST:  in PerformDAGCombine()