Searched refs:TmpVGPR (Results 1 – 2 of 2) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 812 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
814 if (!TmpVGPR) in emitPrologue()
817 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
830 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
832 if (!TmpVGPR) in emitPrologue()
1027 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1029 if (!TmpVGPR) in emitEpilogue()
1034 .addReg(TmpVGPR, RegState::Kill); in emitEpilogue()
1053 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1055 if (!TmpVGPR) in emitEpilogue()
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| H A D | SIRegisterInfo.cpp | 88 Register TmpVGPR = AMDGPU::NoRegister; member
166 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false); in prepare()
170 if (TmpVGPR) { in prepare()
176 TmpVGPR = AMDGPU::VGPR0; in prepare()
195 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
206 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
232 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
240 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
1398 SB.TmpVGPR) in spillSGPR()
1401 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillSGPR()
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