Lines Matching refs:TmpVGPR
812 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
814 if (!TmpVGPR) in emitPrologue()
817 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
820 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
830 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
832 if (!TmpVGPR) in emitPrologue()
835 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
838 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
1027 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1029 if (!TmpVGPR) in emitEpilogue()
1031 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1034 .addReg(TmpVGPR, RegState::Kill); in emitEpilogue()
1053 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1055 if (!TmpVGPR) in emitEpilogue()
1057 buildEpilogRestore(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitEpilogue()
1060 .addReg(TmpVGPR, RegState::Kill); in emitEpilogue()