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Searched refs:SubReg (Results 1 – 25 of 73) sorted by relevance

123

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp196 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
202 LastDefReg = SubReg; in FindLastPartialDef()
289 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
338 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
369 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
451 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
458 if (Live.count(SubReg)) in HandlePhysRegDef()
460 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { in HandlePhysRegDef()
473 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
474 if (!Live.count(SubReg)) in HandlePhysRegDef()
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H A DLiveIntervalCalc.cpp68 unsigned SubReg = MO.getSubReg(); in calculate() local
69 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
70 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
168 unsigned SubReg = MO.getSubReg(); in extendToUses() local
169 if (SubReg != 0) { in extendToUses()
170 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DPeepholeOptimizer.cpp298 addSource(Reg, SubReg); in ValueTrackerResult()
333 return RegSrcs[Idx].SubReg; in getSrcSubReg()
758 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
792 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1074 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1136 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1147 LookupSrc.SubReg = Res.getSrcSubReg(0); in getNewSource()
1258 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1260 if (Def.SubReg) { in rewriteSource()
1976 BaseReg.SubReg) in getNextSourceFromInsertSubreg()
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H A DDetectDeadLanes.cpp174 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
175 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
424 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
447 if (SubReg == 0) in determineInitialUsedLanes()
450 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
457 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
458 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveIntervals.cpp577 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
578 if (SubReg != 0) { in shrinkToUses()
579 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
796 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
797 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1036 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1037 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1463 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1464 if (SubReg != 0 && LaneMask.any() in findLastUseBefore()
1603 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
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H A DMachineInstrBundle.cpp198 unsigned SubReg = *SubRegs; in finalizeBundle() local
199 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
200 LocalDefs.push_back(SubReg); in finalizeBundle()
H A DScheduleDAGInstrs.cpp340 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
341 if (Uses.contains(*SubReg)) in addPhysRegDeps()
342 Uses.eraseAll(*SubReg); in addPhysRegDeps()
344 Defs.eraseAll(*SubReg); in addPhysRegDeps()
376 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
377 if (SubReg == 0) in getLaneMaskForMO()
379 return TRI->getSubRegIndexLaneMask(SubReg); in getLaneMaskForMO()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
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H A DAArch64RegisterInfo.cpp278 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
280 SubReg.isValid(); ++SubReg) { in UpdateCustomCallPreservedMask()
283 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); in UpdateCustomCallPreservedMask()
785 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h246 unsigned SubReg,
297 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
319 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
320 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
324 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
325 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
H A DSIShrinkInstructions.cpp394 Register Reg, unsigned SubReg, in instAccessReg() argument
404 LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) & in instAccessReg()
414 unsigned Reg, unsigned SubReg, in instReadsReg() argument
416 return instAccessReg(MI->uses(), Reg, SubReg, TRI); in instReadsReg()
420 unsigned Reg, unsigned SubReg, in instModifiesReg() argument
422 return instAccessReg(MI->defs(), Reg, SubReg, TRI); in instModifiesReg()
567 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
568 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
569 .addReg(Y1.Reg, 0, Y1.SubReg) in matchSwap()
570 .addReg(X1.Reg, 0, X1.SubReg).getInstr(); in matchSwap()
H A DSIPreAllocateWWMRegs.cpp132 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
133 if (SubReg != 0) { in rewriteRegs()
134 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
H A DSIRegisterInfo.cpp1162 Register SubReg = e == 1 in buildSpillLoadStore() local
1215 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1221 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1240 SubReg = TmpReg; in buildSpillLoadStore()
1340 Register SubReg = in spillSGPR() local
1391 Register SubReg = in spillSGPR() local
1399 .addReg(SubReg, SubKillState) in spillSGPR()
1453 Register SubReg = in restoreSGPR() local
1487 Register SubReg = in restoreSGPR() local
2337 unsigned SubReg, in shouldCoalesce() argument
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/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp254 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
348 for (const auto &SubReg : Map) in computeSubRegs() local
350 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
355 if (SubReg.second == this) { in computeSubRegs()
369 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
370 if (Ins->second == SubReg.first) in computeSubRegs()
473 const CodeGenRegister *SubReg; in computeSecondarySubRegs() local
549 for (auto SubReg : SubRegs) in computeSuperRegs() local
555 for (auto SubReg : SubRegs) { in computeSuperRegs() local
580 for (auto SubReg : SubRegs) in addSubRegsPreOrder() local
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h479 unsigned SubReg; member
481 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
482 : Reg(Reg), SubReg(SubReg) {} in Reg()
485 return Reg == P.Reg && SubReg == P.SubReg;
498 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
500 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2020 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2027 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
H A DMachineInstrBuilder.h98 unsigned SubReg = 0) const {
108 SubReg,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
124 unsigned SubReg = 0) const {
127 return addReg(RegNo, Flags, SubReg);
H A DTargetRegisterInfo.h1029 unsigned SubReg, in shouldCoalesce() argument
1119 unsigned SubReg = 0; variable
1139 unsigned getSubReg() const { return SubReg; } in getSubReg()
1150 SubReg = *Idx++;
1151 if (!SubReg)
H A DMachineFunction.h495 unsigned SubReg; ///< Optional subreg qualifier within Reg.
496 DebugPHIRegallocPos(MachineBasicBlock *MBB, Register Reg, unsigned SubReg)
497 : MBB(MBB), Reg(Reg), SubReg(SubReg) {}
507 unsigned SubReg = 0);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td40 class GP8<GPR SubReg, string n> : PPCReg<n> {
41 let HWEncoding = SubReg.HWEncoding;
42 let SubRegs = [SubReg];
47 class SPE<GPR SubReg, string n> : PPCReg<n> {
48 let HWEncoding = SubReg.HWEncoding;
49 let SubRegs = [SubReg];
71 class VR<VF SubReg, string n> : PPCReg<n> {
74 let SubRegs = [SubReg];
80 class VSRL<FPR SubReg, string n> : PPCReg<n> {
81 let HWEncoding = SubReg.HWEncoding;
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp543 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
544 Reserved.set(SubReg); in getReservedRegs()
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
551 Reserved.set(SubReg); in getReservedRegs()
555 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
556 Reserved.set(SubReg); in getReservedRegs()
569 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
570 Reserved.set(SubReg); in getReservedRegs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp87 unsigned SubReg; member
98 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
640 if (DefR.SubReg) { in visitPHI()
1091 if (!R.SubReg) { in getCell()
1943 assert(!DefR.SubReg); in evaluate()
2211 if (!R.SubReg) { in evaluate()
2218 if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi) in evaluate()
2303 if (PR.SubReg) in evaluate()
3000 if (R1.SubReg) { in rewriteHexConstUses()
3067 if (SR.SubReg) { in rewriteHexConstUses()
[all …]
H A DHexagonRegisterInfo.h60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h56 unsigned SubReg,

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