Lines Matching refs:SubReg
1162 Register SubReg = e == 1 in buildSpillLoadStore() local
1215 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1221 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1235 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
1240 SubReg = TmpReg; in buildSpillLoadStore()
1250 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
1340 Register SubReg = in spillSGPR() local
1352 .addReg(SubReg, getKillRegState(UseKill)) in spillSGPR()
1391 Register SubReg = in spillSGPR() local
1399 .addReg(SubReg, SubKillState) in spillSGPR()
1453 Register SubReg = in restoreSGPR() local
1460 BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1487 Register SubReg = in restoreSGPR() local
1494 SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
2337 unsigned SubReg, in shouldCoalesce() argument
2460 MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg, in findReachingDef() argument
2472 LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg) in findReachingDef()