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Searched refs:SimpleTy (Results 1 – 25 of 62) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h385 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
386 SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16); in is16BitVector()
391 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
392 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
393 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 || in is32BitVector()
399 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
400 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || in is64BitVector()
401 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || in is64BitVector()
412 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); in is128BitVector()
452 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || in isOverloaded()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h49 if (V.SimpleTy != VT.V.SimpleTy)
51 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
67 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
77 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
86 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
131 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
466 return V.SimpleTy; in getRawBits()
475 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
478 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h881 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
912 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
916 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1461 return RegisterTypeForVT[VT.SimpleTy]; in getRegisterType()
2170 RegClassForVT[VT.SimpleTy] = RC; in addRegisterClass()
2199 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift); in setLoadExtAction()
2200 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift; in setLoadExtAction()
2208 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action; in setTruncStoreAction()
2269 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
3056 unsigned Ty = (unsigned)VT.SimpleTy; in setIndexedModeAction()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp133 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32)) in CC_AArch64_Custom_Block()
135 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
137 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
141 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
162 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1; in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp319 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1142 switch (RetVT.SimpleTy) { in emitAddSub()
1161 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1455 switch (VT.SimpleTy) { in emitCmp()
1810 switch (VT.SimpleTy) { in emitLoad()
2040 switch (VT.SimpleTy) { in emitStoreRelease()
2099 switch (VT.SimpleTy) { in emitStore()
2658 switch (VT.SimpleTy) { in selectSelect()
4018 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4121 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1076 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1103 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1320 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1331 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1773 Value.getNode()->getSimpleValueType(0).SimpleTy; in tryStore()
2125 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
3717 switch (SrcTy.SimpleTy) { in GetConvertOpcode()
3721 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3732 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3743 switch (DestTy.SimpleTy) { in GetConvertOpcode()
[all …]
H A DNVPTXTargetTransformInfo.cpp395 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp177 auto isHvxTy = [this, IncludeBool](MVT SimpleTy) { in isTypeForHVX() argument
178 if (isHVXVectorType(SimpleTy, IncludeBool)) in isTypeForHVX()
180 auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy); in isTypeForHVX()
189 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() local
190 if (SimpleTy.isValid() && isHvxTy(SimpleTy)) in isTypeForHVX()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h89 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
92 bool V = count(T.SimpleTy); in insert()
93 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
103 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
704 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp77 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
H A DDAGISelMatcherGen.cpp37 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
44 assert((!T.isSimple() || T.getSimple().SimpleTy == VT) && in getRegisterValueType()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp338 switch (VT.SimpleTy) { in X86FastEmitLoad()
1933 switch (VT.SimpleTy) { in X86SelectDivRem()
2677 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2819 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3008 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3121 switch (VT.SimpleTy) { in fastLowerArguments()
3680 switch (VT.SimpleTy) { in X86MaterializeInt()
3700 switch (VT.SimpleTy) { in X86MaterializeInt()
3734 switch (VT.SimpleTy) { in X86MaterializeFP()
3847 switch (VT.SimpleTy) { in fastMaterializeConstant()
[all …]
H A DX86ISelDAGToDAG.cpp4340 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4346 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4351 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4894 switch (NVT.SimpleTy) { in Select()
4971 switch (NVT.SimpleTy) { in Select()
5053 switch (NVT.SimpleTy) { in Select()
5171 switch (NVT.SimpleTy) { in Select()
5179 switch (NVT.SimpleTy) { in Select()
5190 switch (NVT.SimpleTy) { in Select()
5252 switch (NVT.SimpleTy) { in Select()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp138 switch (VT.SimpleTy) { in selectIndexedLoad()
180 switch (VT.SimpleTy) { in selectIndexedProgMemLoad()
388 switch (VT.SimpleTy) { in select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp89 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp305 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
333 switch (VT.SimpleTy) { in tryIndexedLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp323 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
324 switch (SimpleTy) { in LowerFormalArguments()
333 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp132 switch (Type.SimpleTy) { in toValType()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp804 switch (VT.SimpleTy) { in ARMSimplifyAddress()
860 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
906 switch (VT.SimpleTy) { in ARMEmitLoad()
1043 switch (VT.SimpleTy) { in ARMEmitStore()
1378 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1812 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1905 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3042 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.cpp198 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp762 switch (VT.SimpleTy) { in emitLoad()
817 switch (VT.SimpleTy) { in emitStore()
1371 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1832 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1850 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1876 switch (SrcVT.SimpleTy) { in emitIntZExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp497 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
574 switch (VT.SimpleTy) { \ in getSYNC()
960 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); in getTypeConversion()
961 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1259 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1514 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
H A DValueTypes.cpp152 switch (V.SimpleTy) { in getEVTString()
182 switch (V.SimpleTy) { in getTypeForEVT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp485 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp314 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2087 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandIntLibCall()
2122 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandDivRemLibCall()
2183 switch (Node->getSimpleValueType(0).SimpleTy) { in isSinCosLibcallAvailable()
2217 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandSinCosLibCall()
2450 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
2516 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2574 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2617 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy + 1); in PromoteLegalFP_TO_INT_SAT()
4326 switch (Node->getSimpleValueType(0).SimpleTy) { in ConvertNodeToLibcall()

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