Home
last modified time | relevance | path

Searched refs:SOffset (Results 1 – 16 of 16) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp770 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1057 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1091 SOffset = MCRegister(); in buildSpillLoadStore()
1106 SOffset = Reg; in buildSpillLoadStore()
1112 if (!SOffset) { in buildSpillLoadStore()
1122 SOffset = ScratchOffsetReg; in buildSpillLoadStore()
1128 if (!SOffset) in buildSpillLoadStore()
1254 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1258 MIB.addReg(SOffset, SOffsetRegState); in buildSpillLoadStore()
1284 .addReg(SOffset) in buildSpillLoadStore()
[all …]
H A DAMDGPUInstructionSelector.h252 Register &SOffset, int64_t &ImmOffset) const;
257 Register &RSrcReg, Register &SOffset,
261 Register &SOffset, int64_t &Offset) const;
H A DAMDGPUISelDAGToDAG.cpp197 SDValue &SOffset, SDValue &Offset) const;
1468 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUF()
1531 SOffset = in SelectMUBUF()
1602 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUFScratchOffen()
1633 std::tie(VAddr, SOffset) = foldFrameIndex(N0); in SelectMUBUFScratchOffen()
1640 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1667 SOffset = Addr; in SelectMUBUFScratchOffset()
1681 SOffset = Addr.getOperand(0); in SelectMUBUFScratchOffset()
1685 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUFScratchOffset()
2453 SDValue SRsrc, VAddr, SOffset, Offset; in SelectATOMIC_CMP_SWAP() local
[all …]
H A DAMDGPUInstructionSelector.cpp2449 if (SOffset) in selectG_AMDGPU_ATOMIC_CMPXCHG()
3036 I.add(SOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
4107 .addDef(SOffset) in splitIllegalMUBUFOffset()
4192 Register SOffset; in selectMUBUFAddr64() local
4208 if (SOffset) in selectMUBUFAddr64()
4225 Register SOffset; in selectMUBUFOffset() local
4236 if (SOffset) in selectMUBUFOffset()
4252 Register SOffset; in selectMUBUFAddr64Atomic() local
4268 if (SOffset) in selectMUBUFAddr64Atomic()
4285 Register SOffset; in selectMUBUFOffsetAtomic() local
[all …]
H A DAMDGPULegalizerInfo.h148 Register SOffset, unsigned ImmOffset, Register VIndex,
H A DAMDGPURegisterBankInfo.cpp1340 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1341 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1344 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1349 return SOffset + ImmOffset; in setBufferOffsets()
1359 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1364 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1371 if (SOffset == 0) { in setBufferOffsets()
1450 Register SOffset; in applyMappingSBufferLoad() local
1498 .addUse(SOffset) // soffset in applyMappingSBufferLoad()
1816 Register SOffset = MI.getOperand(4).getReg(); in selectStoreIntrinsic() local
[all …]
H A DAMDGPULegalizerInfo.cpp3700 Register VOffset, Register SOffset, in updateBufferMMO() argument
3706 getConstantVRegValWithLookThrough(SOffset, MRI); in updateBufferMMO()
3840 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
3851 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferStore()
3879 .addUse(SOffset) // soffset in legalizeBufferStore()
3921 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
3938 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferLoad()
3980 .addUse(SOffset) // soffset in legalizeBufferLoad()
4120 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
4127 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, *B.getMRI()); in legalizeBufferAtomic()
[all …]
H A DGCNHazardRecognizer.cpp733 const MachineOperand *SOffset = in createsVALUHazard() local
738 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DSILoadStoreOptimizer.cpp88 bool SOffset = false; member
435 Result.SOffset = true; in getRegs()
461 Result.SOffset = true; in getRegs()
551 if (Regs.SOffset) in setMI()
H A DSIInstrInfo.cpp333 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
335 if (SOffset) { in getMemOperandsWithOffsetWidth()
336 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
337 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
339 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
5693 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
5708 .add(*SOffset) in legalizeOperands()
5732 .add(*SOffset) in legalizeOperands()
H A DSIISelLowering.cpp6785 SDValue SOffset, SDValue Offset, in updateBufferMMO() argument
6787 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in updateBufferMMO()
6804 cast<ConstantSDNode>(SOffset)->getSExtValue() + in updateBufferMMO()
7911 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7912 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
7915 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
7923 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7925 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
7928 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp729 unsigned SOffset = 0; in getMachineOpValue() local
746 ++SOffset; in getMachineOpValue()
772 : SOffset; in getMachineOpValue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
294 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h894 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPUBaseInfo.cpp1912 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
1947 SOffset = Overflow; in splitMUBUFOffset()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4317 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
4364 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
4406 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
4408 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
4410 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()