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Searched refs:ResVT (Results 1 – 23 of 23) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2201 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2202 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2234 EVT ResVT = N->getValueType(0); in performVectorConvertLowCombine() local
2235 if (ResVT != MVT::v2f64) in performVectorConvertLowCombine()
2382 EVT ResVT; in performVectorTruncZeroCombine() local
2389 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2393 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
2429 EVT ResVT; in performVectorTruncZeroCombine() local
2434 ResVT = MVT::v4i32; in performVectorTruncZeroCombine()
2437 ResVT = MVT::v4f32; in performVectorTruncZeroCombine()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp253 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
1527 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
2292 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
2311 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE_SEQ() local
2334 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
2385 EVT ResVT = N->getValueType(0); in SplitVecOp_INSERT_SUBVECTOR() local
2912 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
2946 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_TO_XINT_SAT() local
3476 EVT ResVT = N->getValueType(0); in WidenVecRes_OverflowOp() local
3493 *DAG.getContext(), ResVT.getVectorElementType(), in WidenVecRes_OverflowOp()
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H A DSelectionDAG.cpp1752 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
1753 return getStepVector(DL, ResVT, One); in getStepVector()
1757 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
1758 if (ResVT.isScalableVector()) in getStepVector()
1760 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
1764 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
1767 return getBuildVector(ResVT, DL, OpsStepConstants); in getStepVector()
10080 EVT ResVT = N->getValueType(0); in UnrollVectorOverflowOp() local
10082 EVT ResEltVT = ResVT.getVectorElementType(); in UnrollVectorOverflowOp()
10087 unsigned NE = ResVT.getVectorNumElements(); in UnrollVectorOverflowOp()
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H A DLegalizeIntegerTypes.cpp264 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
266 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
4993 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
4996 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
4997 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
5002 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DDAGCombiner.cpp6700 EVT ResVT = ExtractFrom.getValueType(); in extractShiftForRotate() local
6702 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); in extractShiftForRotate()
16229 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
16231 TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent()); in canMergeExpensiveCrossRegisterBankCopy()
16235 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
16249 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
16255 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4840 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4848 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4849 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4883 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4884 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4984 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
4986 if (ResVT.isVector()) { in ReplaceINTRINSIC_W_CHAIN()
4989 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceINTRINSIC_W_CHAIN()
4990 EVT EltVT = ResVT.getVectorElementType(); in ReplaceINTRINSIC_W_CHAIN()
5074 DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceINTRINSIC_W_CHAIN()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1625 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedAddReductionCost() local
1626 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedAddReductionCost()
1629 if ((LT.second == MVT::v16i8 && ResVT.getSizeInBits() <= 32) || in getExtendedAddReductionCost()
1631 ResVT.getSizeInBits() <= (IsMLA ? 64 : 32)) || in getExtendedAddReductionCost()
1632 (LT.second == MVT::v4i32 && ResVT.getSizeInBits() <= 64)) in getExtendedAddReductionCost()
H A DARMISelLowering.cpp15975 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
16041 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
16046 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
16078 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
16136 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
16139 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
16152 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
16155 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
16170 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
16173 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMISelLowering.h616 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp15006 EVT ResVT = N->getValueType(0); in performUzpCombine() local
15052 EVT ResVT = N->getValueType(0); in performGLD1Combine() local
15938 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
15962 EVT ResVT = N->getValueType(0); in performSelectCombine() local
15967 if (ResVT.isScalableVector()) in performSelectCombine()
15987 if (!ResVT.isVector() || NumMaskElts == 0) in performSelectCombine()
15996 if (CCVT.getSizeInBits() != ResVT.getSizeInBits()) in performSelectCombine()
16842 EVT ResVT = N->getValueType(0); in PerformDAGCombine() local
18305 EVT ResVT = SrcVT.getVectorElementType(); in LowerVECREDUCE_SEQ_FADD() local
18377 RdxVT = getPackedSVEVectorVT(ResVT); in LowerReductionToSVE()
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H A DAArch64ISelLowering.h643 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DAArch64InstrInfo.td5358 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
5361 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
5365 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
5378 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
5380 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
5384 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3376 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3383 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3390 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3406 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5751 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
5779 return DAG.getUNDEF(ResVT); in combineExtract()
5809 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
5811 if (VT != ResVT) { in combineExtract()
5813 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
5849 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3565 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3566 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3567 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3572 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.h1302 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DX86ISelLowering.cpp10722 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
10724 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
10781 MVT ResVT = Op.getSimpleValueType(); in LowerCONCAT_VECTORSvXi1() local
10807 MVT ShiftVT = ResVT; in LowerCONCAT_VECTORSvXi1()
10824 SDValue Vec = Zeros ? DAG.getConstant(0, dl, ResVT) : DAG.getUNDEF(ResVT); in LowerCONCAT_VECTORSvXi1()
10846 if (ResVT.getVectorNumElements() >= 16) in LowerCONCAT_VECTORSvXi1()
21335 MVT ResVT = MVT::v4i32; in LowerFP_TO_INT() local
21346 ResVT = MVT::v8i32; in LowerFP_TO_INT()
40795 SAD = DAG.getBitcast(ResVT, SAD); in combineBasicSADPattern()
43225 ResLo = DAG.getBitcast(ResVT, ResLo); in reduceVMULWidth()
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H A DX86ISelDAGToDAG.cpp4461 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM() local
4462 MVT MaskVT = ResVT; in tryVPTESTM()
4517 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID(); in tryVPTESTM()
4520 dl, ResVT, SDValue(CNode, 0), RC); in tryVPTESTM()
H A DX86InstrSSE.td6988 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
6991 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h838 SDValue getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal);
842 SDValue getStepVector(const SDLoc &DL, EVT ResVT);
H A DTargetLowering.h2769 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7834 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
7896 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7915 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7929 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7932 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7939 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
14348 EVT ResVT = Val.getValueType(); in combineStoreFPToInt() local
14350 if (!isTypeLegal(ResVT)) in combineStoreFPToInt()
14358 if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) in combineStoreFPToInt()
14361 if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() || in combineStoreFPToInt()
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H A DPPCISelDAGToDAG.cpp4397 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
4399 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
4401 ResVT, VCmp, VCmp); in trySETCC()
4405 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td322 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;