15975   EVT ResVT = N->getValueType(0);  in PerformVECREDUCE_ADDCombine()  local
16010     if (ResVT != RetTy || N0->getOpcode() != ExtendCode)  in PerformVECREDUCE_ADDCombine()
16019     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
16041     if (ResVT != RetTy)  in PerformVECREDUCE_ADDCombine()
16046             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
16071     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
16078             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
16128     return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
16130     return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
16136     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16139     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16144     return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
16146     return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
16152     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16155     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16160     return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
16162     return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
16170     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16173     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16178     return DAG.getNode(ARMISD::VMLAVps, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
16181     return DAG.getNode(ARMISD::VMLAVpu, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
16189     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16192     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
16210       return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);  in PerformVECREDUCE_ADDCombine()
19982 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()  argument
19984   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
19987   return (Index == 0 || Index == ResVT.getVectorNumElements());  in isExtractSubvectorCheap()