| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 43 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in computeLegalValueVTs() local
45 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 427 Optional<MVT> RegisterVT) const override { in getNumRegisters() argument
430 RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped) in getNumRegisters()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1097 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1142 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1463 MVT RegisterVT; in computeRegisterProperties() local
1466 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1470 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1532 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1546 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1579 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1606 RegisterVT = DestVT; in getVectorTypeBreakdown()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 340 MVT RegisterVT; in getCopyFromPartsVector() local
347 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
357 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
694 MVT RegisterVT; in getCopyToPartsVector() local
700 NumIntermediates, RegisterVT); in getCopyToPartsVector()
794 MVT RegisterVT = in RegsForValue() local
800 RegVTs.push_back(RegisterVT); in RegsForValue()
844 !RegisterVT.isInteger()) in getCopyFromRegs()
991 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands() local
9429 RetTys.append(NumRegs, RegisterVT); in LowerCallTo()
[all …]
|
| H A D | FunctionLoweringInfo.cpp | 395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
399 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
|
| H A D | FastISel.cpp | 1014 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1018 MyFlags.VT = RegisterVT; in lowerCallTo()
|
| H A D | SelectionDAG.cpp | 2168 MVT RegisterVT; in getReducedAlign() local
2171 NumIntermediates, RegisterVT); in getReducedAlign()
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 975 MVT &RegisterVT) const;
982 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
984 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1473 MVT RegisterVT; in getRegisterType() local
1476 NumIntermediates, RegisterVT); in getRegisterType()
1477 return RegisterVT; in getRegisterType()
1498 Optional<MVT> RegisterVT = None) const {
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1101 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1109 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1113 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1114 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1119 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1127 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1131 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1133 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1134 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
1135 unsigned NumElements = RegisterVT.getVectorNumElements(); in analyzeFormalArgumentsCompute()
[all …]
|
| H A D | SIISelLowering.h | 44 unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
| H A D | SIISelLowering.cpp | 977 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
986 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
987 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
993 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
994 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1001 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
1009 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1016 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1017 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1024 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 302 unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
| H A D | MipsISelLowering.cpp | 131 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
133 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
134 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
136 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
138 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); in getVectorTypeBreakdownForCallingConv()
|
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1396 unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
| H A D | X86ISelLowering.cpp | 2160 MVT RegisterVT; in getRegisterTypeForCallingConv() local
2162 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
2164 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
2165 return RegisterVT; in getRegisterTypeForCallingConv()
2178 MVT RegisterVT; in getNumRegistersForCallingConv() local
2180 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
2182 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
2191 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2198 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
2207 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
[all …]
|