340     MVT RegisterVT;  in getCopyFromPartsVector()  local
347           NumIntermediates, RegisterVT);  in getCopyFromPartsVector()
351                                      NumIntermediates, RegisterVT);  in getCopyFromPartsVector()
356     assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");  in getCopyFromPartsVector()
357     assert(RegisterVT.getSizeInBits() ==  in getCopyFromPartsVector()
694   MVT RegisterVT;  in getCopyToPartsVector()  local
700         NumIntermediates, RegisterVT);  in getCopyToPartsVector()
704                                    NumIntermediates, RegisterVT);  in getCopyToPartsVector()
709   assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");  in getCopyToPartsVector()
794     MVT RegisterVT =  in RegsForValue()  local
800     RegVTs.push_back(RegisterVT);  in RegsForValue()
823     MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(  in getCopyFromRegs()  local
832         P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);  in getCopyFromRegs()
834         P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);  in getCopyFromRegs()
844           !RegisterVT.isInteger())  in getCopyFromRegs()
852       unsigned RegSize = RegisterVT.getScalarSizeInBits();  in getCopyFromRegs()
860         Parts[i] = DAG.getConstant(0, dl, RegisterVT);  in getCopyFromRegs()
881                              RegisterVT, P, DAG.getValueType(FromVT));  in getCopyFromRegs()
885                                      RegisterVT, ValueVT, V, CallConv);  in getCopyFromRegs()
906     MVT RegisterVT = isABIMangled() ? TLI.getRegisterTypeForCallingConv(  in getCopyToRegs()  local
911     if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))  in getCopyToRegs()
915                    NumParts, RegisterVT, V, CallConv, ExtendKind);  in getCopyToRegs()
991     MVT RegisterVT = RegVTs[Value];  in AddInlineAsmOperands()  local
993                                            RegisterVT);  in AddInlineAsmOperands()
997       Ops.push_back(DAG.getRegister(TheReg, RegisterVT));  in AddInlineAsmOperands()
1008     MVT RegisterVT = std::get<1>(CountAndVT);  in getRegsAndSizes()  local
1009     TypeSize RegisterSize = RegisterVT.getSizeInBits();  in getRegsAndSizes()
9426       MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);  in LowerCallTo()  local
9428       unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;  in LowerCallTo()
9429       RetTys.append(NumRegs, RegisterVT);  in LowerCallTo()
9491       MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),  in LowerCallTo()  local
9498         MyFlags.VT = RegisterVT;  in LowerCallTo()
9774       MVT RegisterVT = getRegisterTypeForCallingConv(CLI.RetTy->getContext(),  in LowerCallTo()  local
9780                                               NumRegs, RegisterVT, VT, nullptr,  in LowerCallTo()
10065     MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);  in LowerArguments()  local
10066     ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,  in LowerArguments()
10195       MVT RegisterVT = TLI->getRegisterTypeForCallingConv(  in LowerArguments()  local
10203         ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,  in LowerArguments()
10204                  ArgNo, PartBase+i*RegisterVT.getStoreSize().getKnownMinSize());  in LowerArguments()