Home
last modified time | relevance | path

Searched refs:RegClass (Results 1 – 25 of 67) sorted by relevance

123

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td805 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
814 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
851 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
860 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
969 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
978 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
990 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
999 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1314 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1,
1341 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1,
[all …]
H A DRISCVInstrInfoVSDPatterns.td498 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
503 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
527 vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
601 def : Pat<(fvti.Vector (fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
604 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
606 def : Pat<(fvti.Vector (fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
609 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
614 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
619 fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
625 fvti.RegClass:$rd, fvti.RegClass:$rs2)),
[all …]
H A DRISCVInstrInfoVPseudos.td2662 vti.RegClass, vti.RegClass>;
2672 vti.RegClass, vti.RegClass>;
2690 vti.RegClass, ivti.RegClass>;
2739 Vti.RegClass, Vti.RegClass>;
2771 Wti.RegClass, Vti.RegClass>;
2796 Wti.RegClass, Vti.RegClass>;
2833 vti.RegClass, vti.RegClass>;
2888 vti.RegClass, vti.RegClass>;
3005 vti.RegClass, vti.RegClass>;
3044 wti.RegClass, vti.RegClass, vti.RegClass>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
H A DRegisterClassInfo.cpp50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
94 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
160 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
166 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
142 Register NewVReg = MRI->createVirtualRegister(RegClass); in INITIALIZE_PASS_DEPENDENCY()
H A DTargetInstrInfo.cpp53 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
55 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
58 if (RegClass < 0) in getRegClass()
62 return TRI->getRegClass(RegClass); in getRegClass()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
123 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
H A DWebAssemblyRegStackify.cpp106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
107 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
110 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
113 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
118 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
123 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
639 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
640 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
641 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
644 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
677 (outs typeinfo.RegClass:$dst),
678 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
[all …]
H A DX86FrameLowering.cpp799 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
801 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
803 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
805 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
807 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
809 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
813 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
815 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
817 : MRI.createVirtualRegister(RegClass); in emitStackProbeInlineWindowsCoreCLR64()
3204 auto &RegClass = in adjustStackWithPops() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
77 const RCInfo &RCI = RegClass[RC->getID()]; in get()
H A DRegisterScavenging.h157 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
159 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp41 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
42 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
52 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass() argument
57 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
102 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
111 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
112 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
114 if (!RegClass) { in constrainOperandRegClass()
130 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h88 const TargetRegisterClass &RegClass);
104 const TargetRegisterClass &RegClass,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/
H A DWebAssemblyAsmTypeCheck.cpp247 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck()
256 auto VT = WebAssembly::regClassToValType(Op.RegClass); in typeCheck()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp121 bool validateRegister(Record *Reg, Record *RegClass);
141 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
143 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
145 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1913 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1914 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1979 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1980 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2039 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2040 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2041 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2154 const TargetRegisterClass *RegClass = in createEntryPHI() local
2293 Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass); in createIfRegion()
2429 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
[all …]
H A DSIInstrInfo.cpp993 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
994 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
1023 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
3491 if (OpInfo.RegClass < 0) in isImmOperandLegal()
3805 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
3877 if (RegClass != -1) { in verifyInstruction()
4527 auto RegClass = TID.OpInfo[OpNum].RegClass; in getRegClass() local
4548 RegClass = adjustAllocatableRegClass(ST, MF.getRegInfo(), TID, RegClass, in getRegClass()
4550 return RI.getRegClass(RegClass); in getRegClass()
4558 Desc.OpInfo[OpNo].RegClass == -1) { in getOpRegClass()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp528 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
709 RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
713 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
750 RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
H A DARMBaseRegisterInfo.cpp838 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
842 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg))) in eliminateFrameIndex()
846 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass); in eliminateFrameIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1356 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1358 if (!RegClass || !MF.getRegInfo().tracksLiveness()) in canRenameUpToDef()
1375 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1382 if (RegClass->HasDisjunctSubRegs) { in canRenameUpToDef()
1502 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
1503 for (const MCPhysReg &PR : *RegClass) { in tryToFindRegisterToRename()
1514 << TRI->getRegClassName(RegClass) << "\n"); in tryToFindRegisterToRename()
H A DAArch64AsmPrinter.cpp760 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
762 RegClass = &AArch64::ZPRRegClass; in PrintAsmOperand()
764 RegClass = &AArch64::PPRRegClass; in PrintAsmOperand()
766 RegClass = &AArch64::FPR128RegClass; in PrintAsmOperand()
771 return printAsmRegInClass(MO, RegClass, AltName, O); in PrintAsmOperand()

123