992   const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);  in materializeImmediate()  local
993   if (RegClass == &AMDGPU::SReg_32RegClass ||  in materializeImmediate()
994       RegClass == &AMDGPU::SGPR_32RegClass ||  in materializeImmediate()
995       RegClass == &AMDGPU::SReg_32_XM0RegClass ||  in materializeImmediate()
996       RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {  in materializeImmediate()
1002   if (RegClass == &AMDGPU::SReg_64RegClass ||  in materializeImmediate()
1003       RegClass == &AMDGPU::SGPR_64RegClass ||  in materializeImmediate()
1004       RegClass == &AMDGPU::SReg_64_XEXECRegClass) {  in materializeImmediate()
1010   if (RegClass == &AMDGPU::VGPR_32RegClass) {  in materializeImmediate()
1015   if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) {  in materializeImmediate()
1023   if (RI.isSGPRClass(RegClass)) {  in materializeImmediate()
1024     if (RI.getRegSizeInBits(*RegClass) > 32) {  in materializeImmediate()
1033   ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);  in materializeImmediate()
3491   if (OpInfo.RegClass < 0)  in isImmOperandLegal()
3805     int RegClass = Desc.OpInfo[i].RegClass;  in verifyInstruction()  local
3877     if (RegClass != -1) {  in verifyInstruction()
3881       const TargetRegisterClass *RC = RI.getRegClass(RegClass);  in verifyInstruction()
4348           (Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64RegClassID ||  in verifyInstruction()
4349            Desc.OpInfo[DstIdx].RegClass == AMDGPU::VReg_64_Align2RegClassID)) ||  in verifyInstruction()
4351            (Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID ||  in verifyInstruction()
4352             Desc.OpInfo[Src0Idx].RegClass ==  in verifyInstruction()
4527   auto RegClass = TID.OpInfo[OpNum].RegClass;  in getRegClass()  local
4548   RegClass = adjustAllocatableRegClass(ST, MF.getRegInfo(), TID, RegClass,  in getRegClass()
4550   return RI.getRegClass(RegClass);  in getRegClass()
4558       Desc.OpInfo[OpNo].RegClass == -1) {  in getOpRegClass()
4566   unsigned RCID = Desc.OpInfo[OpNo].RegClass;  in getOpRegClass()
4576   unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;  in legalizeOpWithMove()
4667   const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);  in isLegalRegOperand()
4704       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;  in isOperandLegal()
5618     unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;  in legalizeOperands()
6991     const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);  in findUsedSGPR()
7445   const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;  in isBufferSMRD()