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Searched refs:Reg0 (Results 1 – 21 of 21) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h122 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
126 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
128 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp463 unsigned Reg0 = in emitPrologue() local
469 std::swap(Reg0, Reg1); in emitPrologue()
472 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
485 std::swap(Reg0, Reg1); in emitPrologue()
488 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp169 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
231 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
242 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
245 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII() argument
[all …]
H A DMipsMCCodeEmitter.cpp98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
104 if (Reg0 < Reg1) in LowerCompactBranch()
107 if (Reg0 >= Reg1) in LowerCompactBranch()
111 if (Reg1 >= Reg0) in LowerCompactBranch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp237 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
238 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
242 if (Reg0.isVirtual()) { in runOnMachineFunction()
244 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
840 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
844 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h747 uint16_t Reg0 = 0; variable
755 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
761 return Reg0;
766 return Reg0; in isValid()
772 Reg0 = Reg1;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2184 Ops.push_back(Reg0); in SelectVLD()
2370 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2389 Ops.push_back(Reg0); in SelectVST()
2500 Ops.push_back(Reg0); in SelectVLDSTLane()
3043 Ops.push_back(Reg0); in SelectVLDDup()
3365 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3376 getAL(CurDAG, dl), Reg0, Reg0 }; in tryV6T2BitfieldExtractOp()
3784 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
3788 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0, in Select()
3803 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 }; in Select()
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H A DThumb2SizeReduction.cpp756 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
765 if (Reg0 != Reg2) { in ReduceTo2Addr()
768 if (Reg1 != Reg0) in ReduceTo2Addr()
775 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
780 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
787 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
323 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp184 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
206 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
209 Reg0 = Reg2; in commuteInstructionImpl()
211 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
214 Reg0 = Reg1; in commuteInstructionImpl()
228 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2638 Register Reg0; in valuesIdentical() local
2639 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2640 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2650 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2656 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1202 Register Reg0 = MO0.getReg(); in allocateInstruction() local
1204 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1439 printRegName(O, Reg0); in printVectorListTwo()
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1452 printRegName(O, Reg0); in printVectorListTwoSpaced()
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1507 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1554 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ExpandPseudo.cpp467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
471 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
501 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
514 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()
H A DX86InstrInfo.cpp5686 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
5696 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
5697 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp759 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
762 .addImm(Reg0) in InsertSEH()
772 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
774 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
780 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
810 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
813 .addImm(Reg0) in InsertSEH()
821 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
823 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
829 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h754 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
H A DAMDGPUBaseInfo.cpp1488 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect() argument
1489 for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) { in isRegIntersect()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1169 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1179 if (Reg0 == Reg1) { in commuteInstructionImpl()
1199 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1202 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()