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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h20 unsigned Reg; variable
72 return Reg & MCRegister::VirtualRegFlag && !isStackSlot(Reg); in isVirtualRegister()
92 return isVirtualRegister(Reg); in isVirtual()
98 return isPhysicalRegister(Reg); in isPhysical()
104 return virtReg2Index(Reg); in virtRegIndex()
108 return Reg;
111 unsigned id() const { return Reg; } in id()
114 return MCRegister(Reg); in MCRegister()
123 return MCRegister(Reg); in asMCReg()
129 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
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H A DMachineRegisterInfo.h125 return MO->Contents.Reg.Next; in getNextOperandForReg()
429 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; in getVRegName()
437 VReg2Name.grow(Reg); in insertVRegByName()
438 VReg2Name[Reg] = Name.str(); in insertVRegByName()
451 def_iterator DI = def_begin(Reg); in getOneDef()
669 return VRegInfo[Reg].first; in getRegClassOrRegBank()
680 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank()
732 LLT getType(Register Reg) const { in getType() argument
733 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg)) in getType()
734 return VRegToType[Reg]; in getType()
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H A DLiveVariables.h151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
156 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
163 MachineInstr *FindLastRefOrPartRef(Register Reg);
168 MachineInstr *FindLastPartialDef(Register Reg,
211 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterKilled()
247 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterDead()
272 VarInfo &getVarInfo(Register Reg);
284 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
306 bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); } in isPHIJoin() argument
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H A DLiveIntervals.h115 if (hasInterval(Reg)) in getInterval()
116 return *VirtRegIntervals[Reg.id()]; in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() argument
127 VirtRegIntervals[Reg.id()]; in hasInterval()
133 VirtRegIntervals.grow(Reg.id()); in createEmptyInterval()
134 VirtRegIntervals[Reg.id()] = createInterval(Reg); in createEmptyInterval()
135 return *VirtRegIntervals[Reg.id()]; in createEmptyInterval()
145 void removeInterval(Register Reg) { in removeInterval() argument
146 delete VirtRegIntervals[Reg]; in removeInterval()
147 VirtRegIntervals[Reg] = nullptr; in removeInterval()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp60 VRegInfo[Reg].first = RC; in setRegClass()
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
148 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
151 return Reg; in createIncompleteVirtualRegister()
169 return Reg; in createVirtualRegister()
179 return Reg; in cloneVirtualRegister()
193 setType(Reg, Ty); in createGenericVirtualRegister()
196 return Reg; in createGenericVirtualRegister()
208 verifyUseList(Reg); in clearVirtRegs()
438 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn()
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H A DAggressiveAntiDepBreaker.cpp83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
173 unsigned Reg = *I; in StartBlock() local
204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
213 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
230 if (Reg == 0) in IsImplicitDefUse()
315 RegRefs.erase(Reg); in HandleLastUse()
570 SuperReg = Reg; in FindSuitableFreeRegisters()
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H A DLiveVariables.cpp86 VirtRegInfo.grow(Reg); in getVarInfo()
87 return VirtRegInfo[Reg]; in getVarInfo()
362 if (!PhysRegUse[Reg]) { in HandlePhysRegKill()
367 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
424 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
426 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) in HandleRegMask()
445 if (PhysRegDef[Reg] || PhysRegUse[Reg]) { in HandlePhysRegDef()
653 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction()
654 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); in runOnMachineFunction()
656 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); in runOnMachineFunction()
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H A DFixupStatepointCallerSaved.cpp122 return Reg; in performCopyPropagation()
126 return Reg; in performCopyPropagation()
141 return Reg; in performCopyPropagation()
145 return Reg; in performCopyPropagation()
150 return Reg; in performCopyPropagation()
256 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex()
366 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; } in isCalleeSaved() argument
390 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !is_contained(GCRegs, Reg))) in findRegistersToSpill()
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
461 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) { in insertReloads()
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H A DCriticalAntiDepBreaker.cpp71 unsigned Reg = *AI; in StartBlock() local
85 unsigned Reg = *I; in StartBlock() local
89 unsigned Reg = *AI; in StartBlock() local
92 DefIndices[Reg] = ~0u; in StartBlock()
115 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
122 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { in Observe()
186 if (Reg == 0) continue; in PrescanInstruction()
195 Classes[Reg] = NewRC; in PrescanInstruction()
312 if (Reg == 0) continue; in ScanInstruction()
322 Classes[Reg] = NewRC; in ScanInstruction()
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H A DRegisterScavenging.cpp77 SI.Reg = 0; in init()
174 I.Reg = 0; in forward()
189 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in forward()
228 assert((KillRegs.test(Reg) || isUnused(Reg) || in forward()
250 I.Reg = 0; in backward()
273 return Reg; in FindUnusedReg()
384 if (!MRI.isReserved(Reg) && Used.available(Reg) && in findSurvivorBackwards()
402 if (!MRI.isReserved(Reg) && Used.available(Reg)) { in findSurvivorBackwards()
490 Scavenged[SI].Reg = Reg; in spill()
585 return Reg; in scavengeRegisterBackwards()
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H A DLivePhysRegs.cpp96 removeReg(Reg); in stepForward()
103 for (auto Reg : Clobbers) { in stepForward() local
106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
109 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
111 addReg(Reg.first); in stepForward()
141 if (LiveRegs.count(Reg)) in available()
143 if (MRI.isReserved(Reg)) in available()
160 addReg(Reg); in addBlockLiveIns()
275 MBB.addLiveIn(Reg); in addLiveIns()
297 if (Reg == 0) in recomputeLivenessFlags()
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H A DMachineInstrBundle.cpp156 Register Reg = MO.getReg(); in finalizeBundle() local
157 if (!Reg) in finalizeBundle()
179 Register Reg = MO.getReg(); in finalizeBundle() local
180 if (!Reg) in finalizeBundle()
184 LocalDefs.push_back(Reg); in finalizeBundle()
186 DeadDefSet.insert(Reg); in finalizeBundle()
190 KilledDefSet.erase(Reg); in finalizeBundle()
193 DeadDefSet.erase(Reg); in finalizeBundle()
210 Register Reg = LocalDefs[i]; in finalizeBundle() local
213 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); in finalizeBundle()
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H A DRDFRegisters.cpp49 if (UnitInfos[U].Reg != 0) in PhysicalRegisterInfo()
57 UnitInfos[U].Reg = F; in PhysicalRegisterInfo()
62 UI.Reg = F; in PhysicalRegisterInfo()
109 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet()
110 if (isRegMaskId(Reg)) { in getAliasSet()
120 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
168 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
170 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
203 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); in aliasMM()
231 if (RR.Reg == R) in mapTo()
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H A DCalcSpillWeights.cpp39 if (MRI.reg_nodbg_empty(Reg)) in calculateSpillWeightsAndHints()
51 if (MI->getOperand(0).getReg() == Reg) { in copyHint()
83 unsigned Reg = LI.reg(); in isRematerializable() local
84 unsigned Original = VRM.getOriginal(Reg); in isRematerializable()
105 Reg = MI->getOperand(1).getReg(); in isRematerializable()
109 if (!Register::isVirtualRegister(Reg) || VRM.getOriginal(Reg) != Original) in isRematerializable()
167 Register Reg = LI.reg(); in weightCalcHelper() local
203 const Register Reg; in weightCalcHelper() member
208 if (Reg.isPhysical() != Rhs.Reg.isPhysical()) in weightCalcHelper()
209 return Reg.isPhysical(); in weightCalcHelper()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegister.h25 unsigned Reg; variable
28 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
51 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
52 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot()
57 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
58 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister()
62 return Reg;
72 return Reg; in id()
78 bool operator==(const MCRegister &Other) const { return Reg == Other.Reg; }
79 bool operator!=(const MCRegister &Other) const { return Reg != Other.Reg; }
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H A DMCRegisterInfo.h69 unsigned RegNo = unsigned(Reg); in contains()
253 Iter.init(Reg, DiffList); in mc_difflist_iterator()
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
303 : mc_difflist_iterator(Reg, in mc_superreg_iterator()
339 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg)); in sub_and_superregs_inclusive()
598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
615 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator()
647 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
716 : RUIter(Reg, MCRI) { in MCRegUnitMaskIterator()
782 MCRegister Reg;
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
119 if (isVecReg(Reg)) in getInstrVecReg()
125 if (isVecReg(Reg)) in getInstrVecReg()
168 unsigned Reg = 0; in runOnMachineFunction() local
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
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H A DHexagonGenPredicate.cpp56 RegisterSubReg(const Register &Reg) : R(Reg), S(0) {} in RegisterSubReg()
59 return R == Reg.R && S == Reg.S; in operator ==()
63 return R < Reg.R || (R == Reg.R && S < Reg.S); in operator <()
73 RegisterSubReg Reg; member
80 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
228 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
233 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
250 assert(Reg.R.isVirtual()); in getPredRegFor()
277 .addReg(Reg.R, 0, Reg.S); in getPredRegFor()
379 RegisterSubReg Reg(MO); in convertToPredForm() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp172 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
173 HighestVGPRReg = Reg; in analyzeResourceUsage()
181 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
182 HighestAGPRReg = Reg; in analyzeResourceUsage()
193 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
194 HighestSGPRReg = Reg; in analyzeResourceUsage()
227 Register Reg = MO.getReg(); in analyzeResourceUsage() local
228 switch (Reg) { in analyzeResourceUsage()
296 if (AMDGPU::SReg_32RegClass.contains(Reg) || in analyzeResourceUsage()
297 AMDGPU::SReg_LO16RegClass.contains(Reg) || in analyzeResourceUsage()
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H A DSIOptimizeVGPRLiveRange.cpp269 Register Reg = MO.getReg(); in collectCandidateRegisters() local
270 if (Reg.isPhysical() || !TRI->isVectorRegister(*MRI, Reg)) in collectCandidateRegisters()
286 KillsInElse.insert(Reg); in collectCandidateRegisters()
312 for (auto Reg : KillsInElse) { in collectCandidateRegisters() local
313 if (!IsLiveThroughThen(Reg)) in collectCandidateRegisters()
314 CandidateRegs.push_back(Reg); in collectCandidateRegisters()
437 MI->addRegisterKilled(Reg, TRI); in updateLiveRangeInThenRegion()
485 PHI.addReg(Reg).addMBB(Pred); in optimizeLiveRange()
539 PHI.addReg(Reg).addMBB(Pred); in optimizeWaterfallLiveRange()
620 for (auto Reg : CandidateRegs) in runOnMachineFunction() local
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/freebsd-13.1/sys/contrib/dev/acpica/components/hardware/
H A Dhwregs.c168 ACPI_GENERIC_ADDRESS *Reg,
223 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth()
229 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth()
236 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth()
298 if (!Reg) in AcpiHwValidateRegister()
326 if (Reg->AccessWidth > 4) in AcpiHwValidateRegister()
336 BitWidth = ACPI_ROUND_UP (Reg->BitOffset + Reg->BitWidth, AccessWidth); in AcpiHwValidateRegister()
398 BitWidth = Reg->BitOffset + Reg->BitWidth; in AcpiHwRead()
399 BitOffset = Reg->BitOffset; in AcpiHwRead()
492 BitWidth = Reg->BitOffset + Reg->BitWidth; in AcpiHwWrite()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64TargetStreamer.h49 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument
50 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument
51 virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegP() argument
52 virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegPX() argument
54 virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFReg() argument
55 virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegX() argument
56 virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegP() argument
102 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override;
103 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override;
104 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override;
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H A DAArch64WinCOFFStreamer.cpp75 auto Inst = WinEH::Instruction(UnwindCode, Label, Reg, Offset); in emitARM64WinUnwindCode()
103 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveReg(unsigned Reg, in emitARM64WinCFISaveReg() argument
107 emitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in emitARM64WinCFISaveReg()
112 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in emitARM64WinCFISaveRegX()
117 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in emitARM64WinCFISaveRegP()
122 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in emitARM64WinCFISaveRegPX()
127 emitARM64WinUnwindCode(Win64EH::UOP_SaveLRPair, Reg, Offset); in emitARM64WinCFISaveLRPair()
134 emitARM64WinUnwindCode(Win64EH::UOP_SaveFReg, Reg, Offset); in emitARM64WinCFISaveFReg()
139 emitARM64WinUnwindCode(Win64EH::UOP_SaveFRegX, Reg, Offset); in emitARM64WinCFISaveFRegX()
144 emitARM64WinUnwindCode(Win64EH::UOP_SaveFRegP, Reg, Offset); in emitARM64WinCFISaveFRegP()
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H A DAArch64InstPrinter.cpp1248 switch (Reg) { in getNextVectorRegister()
1323 return Reg; in getNextVectorRegister()
1363 if (Reg == 0) in printMatrixTileList()
1399 Reg = FirstReg; in printVectorList()
1401 Reg = FirstReg; in printVectorList()
1403 Reg = FirstReg; in printVectorList()
1410 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()
1562 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) in printMRSSystemRegister()
1563 O << Reg->Name; in printMRSSystemRegister()
1588 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) in printMSRSystemRegister()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
119 return Reg; in getDefReg()
124 return Reg; in getDefReg()
128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
129 return Reg; in getDefReg()
132 return Reg; in getDefReg()
135 return Reg; in getDefReg()
165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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