53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {  in setRegUsed()  argument
54   LiveUnits.addRegMasked(Reg, LaneMask);  in setRegUsed()
77     SI.Reg = 0;  in init()
100 void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) {  in addRegUnits()  argument
101   for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)  in addRegUnits()
105 void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) {  in removeRegUnits()  argument
106   for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)  in removeRegUnits()
139     MCRegister Reg = MO.getReg().asMCReg();  in determineKillsAndDefs()  local
146         addRegUnits(KillRegUnits, Reg);  in determineKillsAndDefs()
150         addRegUnits(KillRegUnits, Reg);  in determineKillsAndDefs()
152         addRegUnits(DefRegUnits, Reg);  in determineKillsAndDefs()
174     I.Reg = 0;  in forward()
188     Register Reg = MO.getReg();  in forward()  local
189     if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))  in forward()
194       if (!isRegUsed(Reg)) {  in forward()
204         for (const MCPhysReg &SubReg : TRI->subregs(Reg))  in forward()
210         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {  in forward()
228       assert((KillRegs.test(Reg) || isUnused(Reg) ||  in forward()
229               isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&  in forward()
250       I.Reg = 0;  in backward()
262 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {  in isRegUsed()  argument
263   if (isReserved(Reg))  in isRegUsed()
265   return !LiveUnits.available(Reg);  in isRegUsed()
269   for (Register Reg : *RC) {  in FindUnusedReg()
270     if (!isRegUsed(Reg)) {  in FindUnusedReg()
271       LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)  in FindUnusedReg()
273       return Reg;  in FindUnusedReg()
281   for (Register Reg : *RC)  in getRegsAvailable()
282     if (!isRegUsed(Reg))  in getRegsAvailable()
283       Mask.set(Reg);  in getRegsAvailable()
383       for (MCPhysReg Reg : AllocationOrder) {  in findSurvivorBackwards()  local
384         if (!MRI.isReserved(Reg) && Used.available(Reg) &&  in findSurvivorBackwards()
385             LiveOut.available(Reg))  in findSurvivorBackwards()
386           return std::make_pair(Reg, MBB.end());  in findSurvivorBackwards()
401         for (MCPhysReg Reg : AllocationOrder) {  in findSurvivorBackwards()  local
402           if (!MRI.isReserved(Reg) && Used.available(Reg)) {  in findSurvivorBackwards()
403             AvilableReg = Reg;  in findSurvivorBackwards()
447 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,  in spill()  argument
460     if (Scavenged[I].Reg != 0)  in spill()
490   Scavenged[SI].Reg = Reg;  in spill()
494   if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {  in spill()
499           TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +  in spill()
503     TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,  in spill()
511     TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,  in spill()
579   MCPhysReg Reg = P.first;  in scavengeRegisterBackwards()  local
582   if (Reg != 0 && SpillBefore == MBB.end()) {  in scavengeRegisterBackwards()
583     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)  in scavengeRegisterBackwards()
585     return Reg;  in scavengeRegisterBackwards()
591   assert(Reg != 0 && "No register left to scavenge!");  in scavengeRegisterBackwards()
598   ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);  in scavengeRegisterBackwards()
600   LiveUnits.removeReg(Reg);  in scavengeRegisterBackwards()
601   LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)  in scavengeRegisterBackwards()
603   return Reg;  in scavengeRegisterBackwards()
684         Register Reg = MO.getReg();  in scavengeFrameVirtualRegsInBlock()  local
688         if (!Register::isVirtualRegister(Reg) ||  in scavengeFrameVirtualRegsInBlock()
689             Register::virtReg2Index(Reg) >= InitialNumVirtRegs)  in scavengeFrameVirtualRegsInBlock()
694         Register SReg = scavengeVReg(MRI, RS, Reg, true);  in scavengeFrameVirtualRegsInBlock()
706       Register Reg = MO.getReg();  in scavengeFrameVirtualRegsInBlock()  local
708       if (!Register::isVirtualRegister(Reg) ||  in scavengeFrameVirtualRegsInBlock()
709           Register::virtReg2Index(Reg) >= InitialNumVirtRegs)  in scavengeFrameVirtualRegsInBlock()
720         Register SReg = scavengeVReg(MRI, RS, Reg, false);  in scavengeFrameVirtualRegsInBlock()