Home
last modified time | relevance | path

Searched refs:RecVec (Results 1 – 11 of 11) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp255 const RecVec Defs = in checkSTIPredicates()
595 RecVec SWDefs, SRDefs; in collectSchedRW()
743 RecVec &WriteDefs, RecVec &ReadDefs) { in splitSchedReadWrites()
757 RecVec WriteDefs; in findRWs()
758 RecVec ReadDefs; in findRWs()
1268 const RecVec *InstDefs = Sets.expand(Rec); in inferFromInstRWs()
1650 static void dumpRecVec(const RecVec &RV) { in dumpRecVec()
1696 RecVec Preds; in inferFromTransitions()
1808 RecVec CheckUnits = in verifyProcResourceGroups()
1813 RecVec OtherUnits = in verifyProcResourceGroups()
[all …]
H A DCodeGenSchedule.h33 using RecVec = std::vector<Record*>; variable
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
229 RecVec ItinDefList;
233 RecVec ItinRWDefs;
240 RecVec WriteResDefs;
241 RecVec ReadAdvanceDefs;
244 RecVec ProcResourceDefs;
439 RecVec ProcResourceDefs;
[all …]
H A DPredicateExpander.h55 using RecVec = std::vector<Record *>; variable
72 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
73 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
74 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
89 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
H A DPredicateExpander.cpp118 const RecVec &Opcodes) { in expandCheckOpcode()
148 const RecVec &Opcodes) { in expandCheckPseudo()
156 const RecVec &Sequence, in expandPredicateSequence()
242 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
256 const RecVec &Cases, in expandOpcodeSwitchStatement()
424 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
H A DSubtargetEmitter.cpp179 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask()
232 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
299 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
312 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
358 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
390 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
404 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
630 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
790 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
932 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
[all …]
H A DDFAPacketizerEmitter.cpp84 void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
193 const RecVec &Itineraries) { in createScheduleClasses()
H A DInstrInfoEmitter.cpp632 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
681 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
H A DRegisterInfoEmitter.cpp1579 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
H A DCodeGenRegisters.cpp752 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/TableGen/
H A DSetTheory.h66 using RecVec = std::vector<Record *>;
97 using ExpandMap = std::map<Record *, RecVec>;
139 const RecVec *expand(Record *Set);
/freebsd-13.1/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp36 using RecVec = SetTheory::RecVec; typedef
230 if (const RecVec *Result = ST.expand(Rec)) in apply()
285 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
308 const RecVec *SetTheory::expand(Record *Set) { in expand()
323 RecVec &EltVec = Expansions[Set]; in expand()