241   const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl");  in checkSTIPredicates()
255   const RecVec Defs =  in checkSTIPredicates()
258     RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");  in checkSTIPredicates()
299     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
305       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
330     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
337       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
404   RecVec RV = Records.getAllDerivedDefinitions("STIPredicate");  in collectSTIPredicates()
440   RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate");  in checkMCInstPredicates()
462   RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");  in collectRetireControlUnits()
477   RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue");  in collectLoadStoreQueueInfo()
521   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
562 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
569     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
575     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
578       RecVec Selected = Variant->getValueAsListOfDefs("Selected");  in scanSchedRW()
595   RecVec SWDefs, SRDefs;  in collectSchedRW()
600     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
611   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
614     RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
625   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
628     RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
640   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
697       } RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
734     RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()
742 static void splitSchedReadWrites(const RecVec &RWDefs,  in splitSchedReadWrites()
743                                  RecVec &WriteDefs, RecVec &ReadDefs) {  in splitSchedReadWrites()
755 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,  in findRWs()
757   RecVec WriteDefs;  in findRWs()
758   RecVec ReadDefs;  in findRWs()
765 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
883   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
931     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
989 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
1046   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
1065       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;  in createInstRWClass()
1067         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);  in createInstRWClass()
1153     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
1193   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
1248       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
1268     const RecVec *InstDefs = Sets.expand(Rec);  in inferFromInstRWs()
1372     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1438       const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1470       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1520     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1650 static void dumpRecVec(const RecVec &RV) {  in dumpRecVec()
1659                            const RecVec &Preds) {  in dumpTransition()
1696     RecVec Preds;  in inferFromTransitions()
1786 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {  in hasSuperGroup()
1790     RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");  in hasSuperGroup()
1808     RecVec CheckUnits =  in verifyProcResourceGroups()
1813       RecVec OtherUnits =  in verifyProcResourceGroups()
1833   RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");  in collectRegisterFiles()
1855     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");  in collectRegisterFiles()
1900   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1905   RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");  in collectProcResources()
1910   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1915   RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");  in collectProcResources()
1924   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in collectProcResources()
2005       const RecVec &InstRWs = SC.InstRWs;  in checkCompleteness()
2039       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
2163   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
2169   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
2178   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()