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Searched refs:Rd (Results 1 – 25 of 44) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td49 // Rd - 64-bit registers.
50 class Rd<bits<5> num, string n, list<Register> subregs,
112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
118 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
119 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
[all …]
H A DHexagonPseudo.td65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
66 "$Rd = CONST32(#$v)", []>;
67 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
68 "$Rd = CONST64(#$v)", []>;
260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
332 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
497 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
501 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
[all …]
H A DHexagonConstExtenders.cpp323 Register Rd; member
497 if (ED.Rd.Reg != 0) in operator <<()
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
1133 if (Rd != Register(Op)) in getOffsetRange()
1162 ED.Rd = MI.getOperand(OpNum-1); in recordExtender()
1182 ED.Rd = MI.getOperand(0); in recordExtender()
1195 ED.Rd = MI.getOperand(0); in recordExtender()
1204 ED.Rd = MI.getOperand(0); in recordExtender()
1278 assert(ED.Rd.Reg != 0); in assignInits()
1903 assert(ED.Rd.Sub == 0 && ExtR.Sub == 0); in replaceInstr()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td445 bits<4> Rd;
458 bits<4> Rd;
484 bits<4> Rd;
497 bits<4> Rd;
523 bits<4> Rd;
533 bits<4> Rd;
554 bits<4> Rd;
568 bits<4> Rd;
582 bits<4> Rd;
595 bits<4> Rd;
[all …]
H A DARMInstrInfo.td1807 bits<4> Rd;
1833 bits<4> Rd;
2191 bits<4> Rd;
2410 bits<4> Rd;
3569 bits<4> Rd;
3583 bits<4> Rd;
3597 bits<4> Rd;
3613 bits<4> Rd;
3627 bits<4> Rd;
4159 "bfc", "\t$Rd, $imm", "$src = $Rd",
[all …]
H A DARMInstrThumb.td910 bits<3> Rd;
912 let Inst{2-0} = Rd;
920 bits<3> Rd;
931 bits<3> Rd;
940 bits<3> Rd;
1204 bits<3> Rd;
1222 bits<4> Rd;
1232 bits<3> Rd;
1244 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1247 bits<3> Rd;
[all …]
H A DARMInstrCDE.td82 dag Rd;
119 bits<4> Rd;
123 let Inst{15-12} = Rd{3-0};
135 bits<4> Rd;
153 bits<4> Rd;
163 let Inst{3-0} = Rd{3-0};
168 let Rd = (outs GPRwithAPSR_NZCVnosp:$Rd);
176 let Rd = (outs CDEDualRegOp:$Rd);
187 let Oops = ops.Rd;
496 let Oops = ops.Rd;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp160 if (Rd == Ra) in addIntraChainConstraint()
186 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
248 if (Rd != Ra) { in addInterChainConstraint()
252 Chains.insert(Rd); in addInterChainConstraint()
257 Chains.insert(Rd); in addInterChainConstraint()
262 const LiveInterval &ld = LIs.getInterval(Rd); in addInterChainConstraint()
265 if (r == Rd) in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); in apply() local
365 if (addIntraChainConstraint(G, Rd, Ra)) in apply()
366 addInterChainConstraint(G, Rd, Ra); in apply()
[all …]
H A DAArch64InstrFormats.td1937 bits<5> Rd;
1973 bits<5> Rd;
1983 : I<(outs GPR64:$Rd), (ins GPR64:$src), asm, "\t$Rd", "$Rd = $src",
1985 bits<5> Rd;
1999 bits<5> Rd;
2011 : I<(outs GPR64:$Rd), (ins GPR64:$Rn), asm, "\t$Rd", "$Rd = $Rn", []>, Sched<[]> {
2341 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
2540 // add Rd, Rb, -imm -> sub Rd, Rn, imm
6940 "\t$Rd, $Rn", "$Rd = $dst", pat>,
7967 "{\t$Rd.4s, $Rn.8h, $Rm.h$idx}", "$Rd = $dst",
[all …]
H A DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64InstrInfo.td1358 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>;
1363 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movw_symbol_g0:$sym, 0)>;
1371 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movw_symbol_g0:$sym, 0)>;
1996 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
3827 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
3829 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
3831 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
3835 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
3837 def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;
3838 def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>;
[all …]
H A DAArch64SchedPredicates.td347 [// MOV {Rd, SP}, {SP, Rn} =>
348 // ADD {Rd, SP}, {SP, Rn}, #0
361 // MOV Rd, Rm =>
362 // ORR Rd, ZR, Rm, LSL #0
430 [// ORR Rd, ZR, #0
H A DAArch64InstrAtomics.td412 let Constraints = "@earlyclobber $Rd,@earlyclobber $scratch",
414 def CMP_SWAP_8 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
418 def CMP_SWAP_16 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
422 def CMP_SWAP_32 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
426 def CMP_SWAP_64 : Pseudo<(outs GPR64:$Rd, GPR32:$scratch),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td409 "mov\t$imm16, $Rd",
543 "ld\t$src, $Rd",
583 "mov\t$imm, $Rd",
642 "st\t$Rd, $dst",
693 let Rd = R2.Num;
736 let Rd = PC.Num;
778 [(set (i32 GPR:$Rd),
792 let Rd = PC.Num;
799 let Rd = PC.Num;
814 "popc\t$Rs1, $Rd",
[all …]
H A DLanaiInstrFormats.td90 bits<5> Rd;
98 let Inst{27 - 23} = Rd;
150 bits<5> Rd;
158 let Inst{27 - 23} = Rd;
198 bits<5> Rd;
209 let Inst{27 - 23} = Rd;
259 bits<5> Rd;
428 bits<5> Rd;
456 bits<5> Rd;
501 bits<5> Rd;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td393 // ADDW Rd+1:Rd, Rr+1:Rr
476 // SUBIW Rd+1:Rd, K+1:K
693 // ANDI Rd+1:Rd, K+1:K
711 // ORIW Rd+1:Rd, K+1,K
736 // COMW Rd+1:Rd
753 // NEGW Rd+1:Rd
1186 // LDW Rd+1:Rd, P
1212 // LDW Rd+1:Rd, P+
1230 // LDW Rd+1:Rd, -P
1254 // LDDW Rd+1:Rd, P+q
[all …]
H A DAVRDevices.td32 // `LDS Rd, K`
55 // The device supports `ADDI Rd, K`, `SUBI Rd, K`.
74 // The device supports the `LPM Rd, Z[+] instruction.
76 "The device supports the `LPM Rd, Z[+]` "
83 // The device supports the `ELPM Rd, Z[+]` instructions.
85 "The device supports the `ELPM Rd, Z[+]` "
/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1174 Rd = 7; in EmulateADDRdSPImm()
1234 Rd = 7; in EmulateMOVRdSP()
1237 Rd = 12; in EmulateMOVRdSP()
1339 if (Rd == 13) in EmulateMOVRdRm()
2400 uint32_t Rd; in EmulateSUBSPImm() local
2405 Rd = 13; in EmulateSUBSPImm()
3857 Rn = Rd; in EmulateShiftReg()
5972 uint32_t Rd; in EmulateADR() local
6056 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) in EmulateANDImm()
8863 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) in EmulateEORImm()
[all …]
H A DEmulateInstructionARM.h200 const uint32_t Rd, bool setflags,
205 const uint32_t Rd) { in WriteCoreReg() argument
207 return WriteCoreRegOptionalFlags(context, result, Rd, false); in WriteCoreReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td197 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
198 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
199 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
200 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
201 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
202 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
203 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
204 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
205 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
206 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2711 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLDInstruction()
3038 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVSTInstruction()
3308 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD1DupInstruction()
3355 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD2DupInstruction()
3403 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD3DupInstruction()
3438 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD4DupInstruction()
3491 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVMOVModImmInstruction()
3590 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVSHLMaxInstruction()
3633 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeTBLInstruction()
4808 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) in DecodeDoubleRegStore()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp988 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
1079 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
1141 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1683 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1740 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1771 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1810 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1827 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1846 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
1861 if (Rd == 31 && !S) in DecodeAddSubImmShift()
[all …]
/freebsd-13.1/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cpp48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp396 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
398 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs2()
406 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
408 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); in decodeRVCInstrRdRs1Rs2()

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