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Searched refs:OutMI (Results 1 – 25 of 38) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
219 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
244 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchLUi()
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
278 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
302 lowerLongBranchLUi(MI, OutMI); in lowerLongBranch()
306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu); in lowerLongBranch()
310 lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu); in lowerLongBranch()
316 if (lowerLongBranch(MI, OutMI)) in Lower()
319 OutMI.setOpcode(MI->getOpcode()); in Lower()
[all …]
H A DMipsMCInstLower.h37 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
196 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst()
209 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI)) in lowerRISCVMachineInstrToMCInst()
212 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst()
217 OutMI.addOperand(MCOp); in lowerRISCVMachineInstrToMCInst()
220 switch (OutMI.getOpcode()) { in lowerRISCVMachineInstrToMCInst()
235 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
236 OutMI.addOperand(MCOperand::createImm( in lowerRISCVMachineInstrToMCInst()
238 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp51 void lower(const MachineInstr *MI, MCInst &OutMI) const;
61 void lower(const MachineInstr *MI, MCInst &OutMI) const;
158 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
162 OutMI.addOperand(Dest); in lower()
163 OutMI.addOperand(Src); in lower()
177 OutMI.setOpcode(MCOpcode); in lower()
182 OutMI.addOperand(MCOp); in lower()
186 if (FIIdx >= (int)OutMI.getNumOperands()) in lower()
187 OutMI.addOperand(MCOperand::createImm(0)); in lower()
334 OutMI.setOpcode(MI->getOpcode()); in lower()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp44 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
188 MCInst &OutMI) const { in lower()
189 OutMI.setOpcode(MI->getOpcode()); in lower()
293 OutMI.addOperand(MCOp); in lower()
297 removeRegisterOperands(MI, OutMI); in lower()
299 OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs())); in lower()
320 auto RegOpcode = OutMI.getOpcode(); in removeRegisterOperands()
323 OutMI.setOpcode(StackOpcode); in removeRegisterOperands()
326 for (auto I = OutMI.getNumOperands(); I; --I) { in removeRegisterOperands()
327 auto &MO = OutMI.getOperand(I - 1); in removeRegisterOperands()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp528 OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg)); in Lower()
616 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) { in Lower()
683 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); in Lower()
688 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) { in Lower()
755 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); in Lower()
773 OutMI = MCInst(); in Lower()
803 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
809 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
817 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
946 std::swap(OutMI.getOperand(1), OutMI.getOperand(2)); in Lower()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.cpp302 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
303 OutMI.setOpcode(MI->getOpcode()); in Lower()
308 OutMI.addOperand(MCOp); in Lower()
311 switch (OutMI.getOpcode()) { in Lower()
313 OutMI = MCInst(); in Lower()
314 OutMI.setOpcode(AArch64::RET); in Lower()
315 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
318 OutMI = MCInst(); in Lower()
319 OutMI.setOpcode(AArch64::RET); in Lower()
320 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kMCInstLower.cpp145 void M68kMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
147 OutMI.setOpcode(Opcode); in Lower()
154 OutMI.addOperand(MCOp.getValue()); in Lower()
159 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands"); in Lower()
168 OutMI.setOpcode(Opcode); in Lower()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMCInstLower.cpp47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
48 OutMI.setOpcode(MI->getOpcode()); in Lower()
81 OutMI.addOperand(MCOp); in Lower()
H A DBTFDebug.cpp1235 bool BTFDebug::InstLower(const MachineInstr *MI, MCInst &OutMI) { in InstLower() argument
1257 OutMI.setOpcode(BPF::LD_imm64); in InstLower()
1259 OutMI.setOpcode(BPF::MOV_ri); in InstLower()
1260 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in InstLower()
1261 OutMI.addOperand(MCOperand::createImm(Imm)); in InstLower()
1274 OutMI.setOpcode(MI->getOperand(1).getImm()); in InstLower()
1276 OutMI.addOperand(MCOperand::createImm(MI->getOperand(0).getImm())); in InstLower()
1278 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in InstLower()
1279 OutMI.addOperand(MCOperand::createReg(MI->getOperand(2).getReg())); in InstLower()
1280 OutMI.addOperand(MCOperand::createImm(Imm)); in InstLower()
H A DBPFMCInstLower.h32 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcMCInstLower.cpp94 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
98 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
105 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEMCInstLower.cpp77 void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerVEMachineInstrToMCInst() argument
79 OutMI.setOpcode(MI->getOpcode()); in LowerVEMachineInstrToMCInst()
86 OutMI.addOperand(MCOp); in LowerVEMachineInstrToMCInst()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
95 OutMI.setOpcode(MI->getOpcode()); in lower()
100 OutMI.addOperand(lowerOperand(MO)); in lower()
H A DSystemZMCInstLower.h32 void lower(const MachineInstr *MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp62 void AVRMCInstLower::lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const { in lowerInstruction()
63 OutMI.setOpcode(MI.getOpcode()); in lowerInstruction()
106 OutMI.addOperand(MCOp); in lowerInstruction()
H A DAVRMCInstLower.h31 void lowerInstruction(const MachineInstr &MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCMCInstLower.cpp104 void ARCMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
105 OutMI.setOpcode(MI->getOpcode()); in Lower()
112 OutMI.addOperand(MCOp); in Lower()
H A DARCMCInstLower.h33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMCInstLower.cpp103 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
104 OutMI.setOpcode(MI->getOpcode()); in Lower()
111 OutMI.addOperand(MCOp); in Lower()
H A DXCoreMCInstLower.h30 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430MCInstLower.cpp115 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
116 OutMI.setOpcode(MI->getOpcode()); in Lower()
157 OutMI.addOperand(MCOp); in Lower()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMCInstLower.cpp93 void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
94 OutMI.setOpcode(MI->getOpcode()); in Lower()
136 OutMI.addOperand(MCOp); in Lower()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp123 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerARMMachineInstrToMCInst() argument
125 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
163 OutMI.addOperand(MCOp); in LowerARMMachineInstrToMCInst()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMCInstLower.cpp151 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPPCMachineInstrToMCInst() argument
153 OutMI.setOpcode(MI->getOpcode()); in LowerPPCMachineInstrToMCInst()
158 OutMI.addOperand(MCOp); in LowerPPCMachineInstrToMCInst()

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