Lines Matching refs:OutMI
133 MCInst &OutMI) { in lowerRISCVVMachineInstrToMCInst() argument
139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
196 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst()
202 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst()
207 bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in lowerRISCVMachineInstrToMCInst() argument
209 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI)) in lowerRISCVMachineInstrToMCInst()
212 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst()
217 OutMI.addOperand(MCOp); in lowerRISCVMachineInstrToMCInst()
220 switch (OutMI.getOpcode()) { in lowerRISCVMachineInstrToMCInst()
235 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
236 OutMI.addOperand(MCOperand::createImm( in lowerRISCVMachineInstrToMCInst()
238 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
242 OutMI.addOperand( in lowerRISCVMachineInstrToMCInst()
244 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()