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Searched refs:Order (Results 1 – 25 of 136) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-tapi-diff/
H A DDiffEngine.cpp24 StringRef setOrderIndicator(InterfaceInputOrder Order) { in setOrderIndicator() argument
25 return ((Order == lhs) ? "< " : "> "); in setOrderIndicator()
57 OS << Indent << "\t" << setOrderIndicator(Order) in print()
121 InterfaceInputOrder Order) { in addDiffForTargSlice() argument
129 ValTypeT NewVal(Order, Val); in addDiffForTargSlice()
133 ValTypeT NewVal(Order, Val); in addDiffForTargSlice()
147 IRef.getInstallName(), Targ, Diff, Order); in getSingleAttrDiff()
190 Output.push_back(getSingleAttrDiff(Val, Name, Order)); in diffAttribute()
210 Order, Interface->isInstallAPI())); in getSingleIF()
220 Order); in getSingleIF()
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H A DDiffEngine.h65 DiffScalarVal(InterfaceInputOrder Order, T Val) in DiffScalarVal() argument
66 : AttributeDiff(U), Order(Order), Val(Val){}; in DiffScalarVal()
73 InterfaceInputOrder getOrder() const { return Order; } in getOrder()
77 InterfaceInputOrder Order;
84 SymScalar(InterfaceInputOrder Order, const MachO::Symbol *Sym) in SymScalar() argument
85 : Order(Order), Val(Sym){}; in SymScalar()
96 InterfaceInputOrder getOrder() const { return Order; } in getOrder()
100 InterfaceInputOrder Order;
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
59 return AO.Order[Pos];
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
92 : Hints(std::move(Hints)), Order(Order), in AllocationOrder()
93 IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {} in AllocationOrder()
102 assert(OrderLimit <= Order.size()); in getOrderLimitEnd()
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
49 assert(is_contained(Order, Hints[I]) && in create()
52 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
H A DRegAllocGreedy.cpp823 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
840 if (Order.isHint(Hint)) { in tryAssign()
873 auto Order = in canReassign() local
876 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in canReassign()
1096 for (MCRegister PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1206 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryEvict()
1607 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
1905 for (MCPhysReg PhysReg : Order) { in calculateRegionSplitCost()
2344 for (MCPhysReg PhysReg : Order) { in tryLocalSplit()
2661 for (MCRegister PhysReg : Order) { in tryLastChanceRecoloring()
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H A DRegisterClassInfo.cpp100 if (!RCI.Order) in compute()
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
127 RCI.Order[N++] = PhysReg; in compute()
140 RCI.Order[N++] = PhysReg; in compute()
160 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
H A DLocalStackSlotAllocation.cpp59 unsigned Order; member in __anond43b4b110111::FrameRef
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
66 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
302 unsigned Order = 0; in insertFrameReferenceRegisters() local
330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
H A DTargetRegisterInfo.cpp250 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
251 for (unsigned i = 0; i != Order.size(); ++i) in getAllocatableSetForRC()
252 R.set(Order[i]); in getAllocatableSetForRC()
422 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
455 if (!is_contained(Order, Phys)) in getRegAllocationHints()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Support/
H A DDynamicLibrary.cpp74 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
75 if (Order & SO_LoadOrder) { in LibLookup()
89 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
90 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
93 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
94 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
103 if (Order & SO_LoadedLast) { in Lookup()
104 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h708 void setIROrder(unsigned Order) { IROrder = Order; }
1058 IROrder(Order), debugLoc(std::move(dl)) {
1087 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1088 assert(Order >= 0 && "bad IROrder");
1408 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1462 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
2235 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2326 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2330 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2436 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
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H A DScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator
124 : Dep(S, Order), Contents(), Latency(0) { in SDep()
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
195 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
201 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
207 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
473 case Order: in overlaps()
H A DRegisterClassInfo.h37 std::unique_ptr<MCPhysReg[]> Order; member
42 return makeArrayRef(Order.get(), NumRegs);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h148 unsigned Order; variable
162 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), in SDDbgValue()
218 unsigned getOrder() const { return Order; } in getOrder()
244 unsigned Order; variable
248 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
258 unsigned getOrder() const { return Order; } in getOrder()
H A DScheduleDAGSDNodes.cpp761 if (Order != 0 && DVOrder != Order) in ProcessSDDbgValues()
786 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
787 if (!Order || Seen.count(Order)) { in ProcessSourceNode()
799 Seen.insert(Order); in ProcessSourceNode()
800 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
805 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
979 unsigned Order = Orders[i].first; in EmitSchedule() local
984 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1002 LastOrder = Order; in EmitSchedule()
1025 unsigned Order = InstrOrder.first; in EmitSchedule() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp251 SmallVector<RegionNode *, 8> Order; member in __anon4b9e022b0111::StructurizeCFG
375 if (Order.empty()) in INITIALIZE_PASS_DEPENDENCY()
383 unsigned I = 0, E = Order.size(); in INITIALIZE_PASS_DEPENDENCY()
402 Order[I++] = N.first; in INITIALIZE_PASS_DEPENDENCY()
417 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); in INITIALIZE_PASS_DEPENDENCY()
420 EntryNode.first = Order[E - 1]; in INITIALIZE_PASS_DEPENDENCY()
527 for (RegionNode *RN : reverse(Order)) { in collectInfos()
766 if (!Order.empty() || !ExitUseAllowed) in needPostfix()
851 RegionNode *Node = Order.back(); in handleLoops()
907 while (!Order.empty()) { in createFlow()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def147 ArrayRef<PartialMappingIdx> Order) {
148 if (Order.front() != FirstAlias)
150 if (Order.back() != LastAlias)
152 if (Order.front() > Order.back())
155 PartialMappingIdx Previous = Order.front();
157 for (const auto &Current : Order) {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
64 for (MCPhysReg Reg : Order) in addHints()
68 for (MCPhysReg Reg : Order) in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
127 for (MCPhysReg OrderReg : Order) in getRegAllocationHints()
157 addHints(Order, Hints, RC, MRI); in getRegAllocationHints()
178 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
/freebsd-13.1/sys/contrib/device-tree/Bindings/media/
H A Dfsl-vdoa.txt1 Freescale Video Data Order Adapter
4 The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
/freebsd-13.1/contrib/libxo/tests/core/saved/
H A Dtest_01.T.out10 Item Total Sold In Stock On Order SKU
53 Item Total Sold In Stock On Order SKU
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGAtomic.cpp571 Load->setAtomic(Order, Scope); in EmitAtomicOp()
583 Store->setAtomic(Order, Scope); in EmitAtomicOp()
721 Order, CGF.CGM.getLLVMContext()); in EmitAtomicOp()
723 Order, SCID); in EmitAtomicOp()
749 Order, in EmitAtomicOp()
829 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
1091 Args.add(RValue::get(Order), getContext().IntTy); in EmitAtomicExpr()
1092 Order = OrderFail; in EmitAtomicExpr()
1244 Args.add(RValue::get(Order), in EmitAtomicExpr()
1297 if (isa<llvm::ConstantInt>(Order)) { in EmitAtomicExpr()
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H A DCGOpenMPRuntime.h552 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo() argument
554 : Flags(Flags), Order(Order), Kind(Kind) {} in OffloadEntryInfo()
558 bool isValid() const { return Order != ~0u; } in isValid()
559 unsigned getOrder() const { return Order; } in getOrder()
580 unsigned Order = ~0u; variable
613 explicit OffloadEntryInfoTargetRegion(unsigned Order, in OffloadEntryInfoTargetRegion() argument
617 : OffloadEntryInfo(OffloadingEntryInfoTargetRegion, Order, Flags), in OffloadEntryInfoTargetRegion()
635 unsigned Order);
674 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar() argument
678 unsigned Order, llvm::Constant *Addr, CharUnits VarSize, in OffloadEntryInfoDeviceGlobalVar() argument
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Bitcode/Writer/
H A DValueEnumerator.cpp834 SmallVector<MDIndex, 64> Order; in organizeMetadata() local
835 Order.reserve(MetadataMap.size()); in organizeMetadata()
837 Order.push_back(MetadataMap.lookup(MD)); in organizeMetadata()
845 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) { in organizeMetadata()
855 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) { in organizeMetadata()
856 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
864 if (MDs.size() == Order.size()) in organizeMetadata()
871 for (unsigned I = MDs.size(), E = Order.size(), ID = MDs.size(); I != E; in organizeMetadata()
873 unsigned F = Order[I].F; in organizeMetadata()
885 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
/freebsd-13.1/contrib/file/
H A DRELEASE-PROCEDURE20 - Change the "Date Order" to the current time
25 - Set the "Date Order" to 2030-01-01 (i.e. far in the future)
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h519 unsigned Order = 0; // Cache the sort key. member
746 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt() argument
747 return RegUnitSetOrder[Order]; in getRegSetIDAt()
750 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt() argument
751 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h308 std::vector<std::string> &getOrder() { return Order; } in getOrder()
309 const std::vector<std::string> &getOrder() const { return Order; } in getOrder()
329 std::vector<std::string> Order;

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