10b57cec5SDimitry Andric //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file implements an allocation order for virtual registers.
100b57cec5SDimitry Andric //
110b57cec5SDimitry Andric // The preferred allocation order for a virtual register depends on allocation
120b57cec5SDimitry Andric // hints and target hooks. The AllocationOrder class encapsulates all of that.
130b57cec5SDimitry Andric //
140b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
150b57cec5SDimitry Andric
160b57cec5SDimitry Andric #include "AllocationOrder.h"
170b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
180b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
190b57cec5SDimitry Andric #include "llvm/CodeGen/RegisterClassInfo.h"
200b57cec5SDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
210b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
220b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
230b57cec5SDimitry Andric
240b57cec5SDimitry Andric using namespace llvm;
250b57cec5SDimitry Andric
260b57cec5SDimitry Andric #define DEBUG_TYPE "regalloc"
270b57cec5SDimitry Andric
280b57cec5SDimitry Andric // Compare VirtRegMap::getRegAllocPref().
create(unsigned VirtReg,const VirtRegMap & VRM,const RegisterClassInfo & RegClassInfo,const LiveRegMatrix * Matrix)29*af732203SDimitry Andric AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
300b57cec5SDimitry Andric const RegisterClassInfo &RegClassInfo,
31*af732203SDimitry Andric const LiveRegMatrix *Matrix) {
320b57cec5SDimitry Andric const MachineFunction &MF = VRM.getMachineFunction();
330b57cec5SDimitry Andric const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
34*af732203SDimitry Andric auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
35*af732203SDimitry Andric SmallVector<MCPhysReg, 16> Hints;
36*af732203SDimitry Andric bool HardHints =
37*af732203SDimitry Andric TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
380b57cec5SDimitry Andric
390b57cec5SDimitry Andric LLVM_DEBUG({
400b57cec5SDimitry Andric if (!Hints.empty()) {
410b57cec5SDimitry Andric dbgs() << "hints:";
420b57cec5SDimitry Andric for (unsigned I = 0, E = Hints.size(); I != E; ++I)
430b57cec5SDimitry Andric dbgs() << ' ' << printReg(Hints[I], TRI);
440b57cec5SDimitry Andric dbgs() << '\n';
450b57cec5SDimitry Andric }
460b57cec5SDimitry Andric });
470b57cec5SDimitry Andric #ifndef NDEBUG
480b57cec5SDimitry Andric for (unsigned I = 0, E = Hints.size(); I != E; ++I)
490b57cec5SDimitry Andric assert(is_contained(Order, Hints[I]) &&
500b57cec5SDimitry Andric "Target hint is outside allocation order.");
510b57cec5SDimitry Andric #endif
52*af732203SDimitry Andric return AllocationOrder(std::move(Hints), Order, HardHints);
530b57cec5SDimitry Andric }
54