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Searched refs:Masked (Results 1 – 25 of 27) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h96 uint16_t Masked : 1; member
106 uint16_t Masked : 1; member
116 uint16_t Masked : 1; member
125 uint16_t Masked : 1; member
134 uint16_t Masked : 1; member
143 uint16_t Masked :1; member
151 uint16_t Masked : 1; member
H A DRISCVInstrInfoVPseudos.td427 bits<1> Masked = M;
444 bits<1> Masked = M;
455 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
460 bits<1> Masked = M;
491 bits<1> Masked = M;
509 bits<1> Masked = M;
527 bits<1> Masked = M;
544 bits<1> Masked = M;
728 RISCVVSE</*Masked*/0, /*Strided*/0, log2<EEW>.val, VLMul> {
742 RISCVVSE</*Masked*/1, /*Strided*/0, log2<EEW>.val, VLMul> {
[all …]
H A DRISCVISelLowering.cpp4777 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING() local
4780 return DAG.getMergeValues({Masked, Chain}, DL); in lowerGET_ROUNDING()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DCaymanInstructions.td116 let DST_SEL_Y = 7; // Masked
117 let DST_SEL_Z = 7; // Masked
118 let DST_SEL_W = 7; // Masked
126 let DST_SEL_Y = 7; // Masked
127 let DST_SEL_Z = 7; // Masked
128 let DST_SEL_W = 7; // Masked
138 let DST_SEL_Y = 7; // Masked
139 let DST_SEL_Z = 7; // Masked
140 let DST_SEL_W = 7; // Masked
H A DEvergreenInstructions.td190 let DST_SEL_Y = 7; // Masked
191 let DST_SEL_Z = 7; // Masked
192 let DST_SEL_W = 7; // Masked
201 let DST_SEL_Y = 7; // Masked
202 let DST_SEL_Z = 7; // Masked
203 let DST_SEL_W = 7; // Masked
214 let DST_SEL_Y = 7; // Masked
215 let DST_SEL_Z = 7; // Masked
216 let DST_SEL_W = 7; // Masked
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp191 Value *Masked, *ShiftShAmt; in dropRedundantMaskingOfLeftShiftInput() local
193 m_Shift(m_Value(Masked), m_ZExtOrSelf(m_Value(ShiftShAmt)))); in dropRedundantMaskingOfLeftShiftInput()
198 if (match(Masked, m_CombineAnd(m_Trunc(m_Value(Masked)), m_Value(Trunc))) && in dropRedundantMaskingOfLeftShiftInput()
203 Type *WidestTy = Masked->getType(); in dropRedundantMaskingOfLeftShiftInput()
225 if (match(Masked, m_c_And(m_CombineOr(MaskA, MaskB), m_Value(X)))) { in dropRedundantMaskingOfLeftShiftInput()
230 if (!canTryToConstantAddTwoShiftAmounts(OuterShift, ShiftShAmt, Masked, in dropRedundantMaskingOfLeftShiftInput()
255 } else if (match(Masked, m_c_And(m_CombineOr(MaskC, MaskD), m_Value(X))) || in dropRedundantMaskingOfLeftShiftInput()
256 match(Masked, m_Shr(m_Shl(m_Value(X), m_Value(MaskShAmt)), in dropRedundantMaskingOfLeftShiftInput()
262 if (!canTryToConstantAddTwoShiftAmounts(OuterShift, ShiftShAmt, Masked, in dropRedundantMaskingOfLeftShiftInput()
303 if (!Masked->hasOneUse()) in dropRedundantMaskingOfLeftShiftInput()
[all …]
H A DInstCombineAndOrXor.cpp828 Value *Masked = Builder.CreateAnd(L1, Mask); in foldAndOrOfICmpsOfAndWithPow2() local
830 return Builder.CreateICmp(NewPred, Masked, Mask); in foldAndOrOfICmpsOfAndWithPow2()
H A DInstCombineCompares.cpp1342 Value *Masked = Builder.CreateAnd(X, Mask); in foldIRemByPowerOfTwoToBitTest() local
1343 return ICmpInst::Create(Instruction::ICmp, Pred, Masked, Zero); in foldIRemByPowerOfTwoToBitTest()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Support/
H A DAPFixedPoint.cpp38 APInt Masked(NewVal & Mask); in convert() local
41 if (!(Masked == Mask || Masked == 0)) { in convert()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp665 Value *Masked = Builder.CreateAnd(Trunc->getOperand(0), Mask); in ConvertTruncs() local
667 if (auto *I = dyn_cast<Instruction>(Masked)) in ConvertTruncs()
670 ReplaceAllUsersOfWith(Trunc, Masked); in ConvertTruncs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemProfiler.cpp427 if (auto *Masked = dyn_cast<ConstantInt>(Vector->getOperand(Idx))) { in instrumentMaskedLoadOrStore() local
428 if (Masked->isZero()) in instrumentMaskedLoadOrStore()
H A DAddressSanitizer.cpp1581 if (auto *Masked = dyn_cast<ConstantInt>(Vector->getOperand(Idx))) { in instrumentMaskedLoadOrStore() local
1582 if (Masked->isZero()) in instrumentMaskedLoadOrStore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1006 Value *Masked = IC.Builder.CreateAnd(Input, II.getArgOperand(1)); in instCombineIntrinsic() local
1007 Value *Shifted = IC.Builder.CreateLShr(Masked, in instCombineIntrinsic()
1054 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic() local
1055 return IC.replaceInstUsesWith(II, Masked); in instCombineIntrinsic()
H A DX86InstrFragmentsSIMD.td704 // Masked versions of above
1076 // Masked store fragments.
H A DX86ISelDAGToDAG.cpp4313 bool FoldedBCast, bool Masked) { in getVPTESTMOpc() argument
4316 if (Masked) \ in getVPTESTMOpc()
H A DX86ISelLowering.cpp12155 if (SDValue Masked = lowerShuffleAsBitMask(DL, VT, V1, V2, Mask, Zeroable, in lowerShuffleAsBlend() local
12157 return Masked; in lowerShuffleAsBlend()
12225 return Masked; in lowerShuffleAsBlend()
14524 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, in lowerV4I32Shuffle() local
14526 return Masked; in lowerV4I32Shuffle()
15233 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, in lowerV8I16Shuffle() local
15235 return Masked; in lowerV8I16Shuffle()
15512 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, in lowerV16I8Shuffle() local
15514 return Masked; in lowerV16I8Shuffle()
18064 if (SDValue Masked = lowerShuffleAsBitMask(DL, MVT::v64i8, V1, V2, Mask, in lowerV64I8Shuffle() local
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsHexagon.td384 // Masked vector stores
H A DIntrinsics.td1506 //===-------------------------- Masked Intrinsics -------------------------===//
/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp742 return TTI::CastContextHint::Masked; in getCastContextHint()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp438 if (CCH == TTI::CastContextHint::Masked && DstTy.getSizeInBits() > 128) in getCastInstrCost()
444 CCH == TTI::CastContextHint::Masked) { in getCastInstrCost()
H A DARMInstrMVE.td7315 // Masked trunc stores
7331 // Masked ext loads
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h1056 Masked, ///< The cast is used with a masked load/store. enumerator
/freebsd-13.1/contrib/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntime.cpp11485 llvm::SmallVector<char, 2> Masked; in emitX86DeclareSimdFunction() local
11488 Masked.push_back('N'); in emitX86DeclareSimdFunction()
11489 Masked.push_back('M'); in emitX86DeclareSimdFunction()
11492 Masked.push_back('N'); in emitX86DeclareSimdFunction()
11495 Masked.push_back('M'); in emitX86DeclareSimdFunction()
11498 for (char Mask : Masked) { in emitX86DeclareSimdFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5961 SDValue Masked = DAG.getNode(ISD::AND, DL, VT, N, IntMax); in prepareSREMEqFold() local
5962 Created.push_back(Masked.getNode()); in prepareSREMEqFold()
5963 SDValue MaskedIsZero = DAG.getSetCC(DL, SETCCVT, Masked, Zero, Cond); in prepareSREMEqFold()
H A DDAGCombiner.cpp2588 bool Masked = false; in getAsCarry() local
2598 Masked = true; in getAsCarry()
2621 if (Masked || in getAsCarry()

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