Home
last modified time | relevance | path

Searched refs:MCSchedClassDesc (Results 1 – 24 of 24) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h47 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
60 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
103 const MCSchedClassDesc *SC = nullptr) const;
106 const MCSchedClassDesc *SC = nullptr) const;
110 const MCSchedClassDesc *SC = nullptr) const;
134 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
138 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
H A DMachineTraceMetrics.h66 struct MCSchedClassDesc;
288 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
289 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
H A DScheduleDAGInstrs.h44 struct MCSchedClassDesc;
265 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
H A DScheduleDAG.h39 struct MCSchedClassDesc;
253 const MCSchedClassDesc *SchedClass =
H A DMachineScheduler.h758 std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
788 unsigned countResource(const MCSchedClassDesc *SC, unsigned PIdx,
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp86 const MCSchedClassDesc *SC) const { in mustBeginGroup()
97 const MCSchedClassDesc *SC) const { in mustEndGroup()
108 const MCSchedClassDesc *SC) const { in getNumMicroOps()
132 const MCSchedClassDesc *TargetSchedModel::
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
229 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
256 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
282 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
312 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
[all …]
H A DMachineCombiner.cpp117 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
391 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
395 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
416 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
417 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
422 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC); in preservesResourceLen()
423 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC); in preservesResourceLen()
H A DMachineTraceMetrics.cpp122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1226 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1227 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1234 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1238 for (const MCSchedClassDesc *SC : Instrs) { in getResourceLength()
H A DMachineScheduler.cpp2026 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU); in init()
2102 SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx, in getNextResourceCycle()
2187 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2344 unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx, in countResource()
2392 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2628 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
H A DMachinePipeliner.cpp1014 const MCSchedClassDesc *SCDesc = in minFuncUnits()
1057 const MCSchedClassDesc *SCDesc = in calcCriticalResources()
3017 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in canReserveResources()
3057 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in reserveResources()
H A DScheduleDAGInstrs.cpp596 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h110 struct MCSchedClassDesc { struct
307 const MCSchedClassDesc *SchedClassTable;
347 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
356 const MCSchedClassDesc &SCDesc);
365 const MCSchedClassDesc &SCDesc);
H A DMCSubtargetInfo.h167 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
171 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
175 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
183 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
205 getReadAdvanceEntries(const MCSchedClassDesc &SC) const { in getReadAdvanceEntries()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp41 const MCSchedClassDesc &SCDesc) { in computeInstrLatency()
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
89 const MCSchedClassDesc &SCDesc) { in getReciprocalThroughput()
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
171 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
272 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
341 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
390 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
418 const MCSchedClassDesc *SC = SchedModel->resolveSchedClass(MI); in emitInstruction()
H A DSystemZHazardRecognizer.h121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
H A DSystemZMachineScheduler.cpp255 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp48 std::vector<std::vector<MCSchedClassDesc>> ProcSchedClasses;
985 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); in GenSchedClassTables()
991 MCSchedClassDesc &SCDesc = SCTab.back(); in GenSchedClassTables()
1011 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
1057 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1090 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1158 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
1179 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1295 std::vector<MCSchedClassDesc> &SCTab = in EmitSchedClassTables()
1308 << MCSchedClassDesc::InvalidNumMicroOps in EmitSchedClassTables()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp39 const MCSchedClassDesc &SCDesc, in initializeUsedResources()
248 const MCSchedClassDesc &SCDesc, in computeMaxLatency()
295 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
566 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
567 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in createInstrDescImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp86 const MCSchedClassDesc *SCDesc = in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp229 const MCSchedClassDesc *SCDesc = in shouldReplaceInst()
234 const MCSchedClassDesc *SCDescRepl; in shouldReplaceInst()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp495 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in collectWrites()
563 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in checkRAWHazards()
626 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp110 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in collectData()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp210 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()