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Searched refs:Load0 (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp133 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr() argument
136 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr()
139 unsigned Opc0 = Load0->getMachineOpcode(); in areLoadsFromSameBasePtr()
149 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
153 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
181 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)); in areLoadsFromSameBasePtr()
184 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
188 dyn_cast<ConstantSDNode>(Load0->getOperand(1)); in areLoadsFromSameBasePtr()
206 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
221 SDValue Off0 = Load0->getOperand(OffIdx0); in areLoadsFromSameBasePtr()
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H A DSIInstrInfo.h199 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
H A DAMDGPURegisterBankInfo.cpp1192 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0); in applyMappingLoad() local
1196 auto Ins0 = B.buildInsert(LoadTy, Undef, Load0, 0); in applyMappingLoad()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1828 SDValue Load0 = DAG.getLoad(SingleTy, dl, Chain, Base0, MOp0); in SplitHvxMemOp() local
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
1833 Load0.getValue(1), Load1.getValue(1)) }, dl); in SplitHvxMemOp()
H A DHexagonISelLowering.cpp3060 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO); in LowerUnalignedLoad() local
3064 {Load1, Load0, BaseNoOff.getOperand(0)}); in LowerUnalignedLoad()
3066 Load0.getValue(1), Load1.getValue(1)); in LowerUnalignedLoad()