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Searched refs:LR (Results 1 – 25 of 176) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeUtils.h26 static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], in DistributeRange() argument
29 typename LiveRangeT::iterator J = LR.begin(), E = LR.end(); in DistributeRange()
40 LR.segments.erase(J, E); in DistributeRange()
43 unsigned j = 0, e = LR.getNumValNums(); in DistributeRange()
47 VNInfo *VNI = LR.getValNumInfo(i); in DistributeRange()
53 LR.valnos[j++] = VNI; in DistributeRange()
56 LR.valnos.resize(j); in DistributeRange()
H A DLiveRangeCalc.cpp83 Updater.setDest(&I.LR); in updateFromLiveIns()
107 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
161 LiveRange::iterator UB = upper_bound(LR, End.getPrevSlot()); in isDefOnEntry()
162 if (UB != LR.begin()) { in isDefOnEntry()
169 if (LR.isUndefIn(Undefs, Seg.end, End)) in isDefOnEntry()
177 if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) { in isDefOnEntry()
249 auto EP = LR.extendInBlock(Undefs, Start, End); in findReachingDefs()
283 LiveRangeUpdater Updater(&LR); in findReachingDefs()
319 addLiveInBlock(LR, DomTree->getNode(MBB)); in findReachingDefs()
400 LiveRange &LR = I.LR; in updateSSA() local
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H A DLiveInterval.cpp67 LiveRange *LR; member in __anon7d11c6fd0111::CalcLiveRangeUtilBase
70 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} in CalcLiveRangeUtilBase() argument
288 CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {} in CalcLiveRangeUtilVector() argument
314 CalcLiveRangeUtilSet(LiveRange *LR) : CalcLiveRangeUtilSetBase(LR) {} in CalcLiveRangeUtilSet() argument
322 LR->segmentSet->insert(LR->segmentSet->end(), S); in insertAtEnd()
1141 if (LR) in print()
1185 LR->addSegmentToSet(Seg); in add()
1255 LR->segments.push_back(Seg); in add()
1256 WriteI = ReadI = LR->end(); in add()
1297 LR->verify(); in flush()
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H A DLiveIntervals.cpp118 for (LiveRange *LR : RegUnitRanges) in releaseMemory()
119 delete LR; in releaseMemory()
320 LR.flushSegmentSet(); in computeRegUnitRange()
346 if (!LR) { in computeLiveInRegUnits()
660 LR.removeSegment(Kill, MBBEnd); in pruneValue()
1092 handleMoveDown(LR); in updateRange()
1096 LR.verify(); in updateRange()
1254 LR.removeValNo(OldIdxVNI); in handleMoveDown()
1574 if (LII == LR.begin()) { in repairOldRegInRange()
1621 LII = LR.begin(); in repairOldRegInRange()
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H A DLiveRegMatrix.cpp178 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, in query() argument
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
200 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference() argument
201 return query(LR, Unit).checkInterference(); in checkInterference()
214 LiveRange LR; in checkInterference() local
215 LR.addSegment(Seg); in checkInterference()
232 Q.reset(UserTag, LR, Matrix[*Units]); in checkInterference()
H A DLiveIntervalCalc.cpp43 LiveRange &LR, const MachineOperand &MO) { in createDeadDef() argument
49 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
133 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) { in createDeadDefs() argument
142 createDeadDef(*Indexes, *Alloc, LR, MO); in createDeadDefs()
145 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg, in extendToUses() argument
203 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
H A DMachineVerifier.cpp518 report_context_liverange(LR); in report_context()
2121 report_context_liverange(LR); in checkLivenessAtUse()
2127 report_context_liverange(LR); in checkLivenessAtUse()
2145 report_context_liverange(LR); in checkLivenessAtDef()
2154 report_context_liverange(LR); in checkLivenessAtDef()
2173 report_context_liverange(LR); in checkLivenessAtDef()
2746 verifyLiveRange(*LR, i); in verifyLiveIntervals()
2759 report_context(LR, Reg, LaneMask); in verifyLiveRangeValue()
2849 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) { in verifyLiveRangeSegment()
3066 for (const VNInfo *VNI : LR.valnos) in verifyLiveRange()
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H A DRegAllocFast.cpp535 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin()
691 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
696 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
745 const Register VirtReg = LR.VirtReg; in allocVirtReg()
746 assert(LR.PhysReg == 0); in allocVirtReg()
824 LR.Error = true; in allocVirtReg()
825 LR.PhysReg = 0; in allocVirtReg()
830 assignVirtToPhysReg(MI, LR, BestReg); in allocVirtReg()
1058 Register VirtReg = LR.VirtReg; in dumpState()
1060 MCPhysReg PhysReg = LR.PhysReg; in dumpState()
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H A DLiveIntervalUnion.cpp141 if (LR->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
147 LRI = LR->begin(); in collectInterferingVRegs()
152 LiveRange::const_iterator LREnd = LR->end(); in collectInterferingVRegs()
179 LRI = LR->advanceTo(LRI, LiveUnionI.start()); in collectInterferingVRegs()
H A DRegisterCoalescer.cpp2335 LiveRange &LR; member in __anon46211ebe0311::JoinVals
2512 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2516 Vals(LR.getNumValNums()) {} in JoinVals()
3055 VNInfo *VNI = LR.getValNumInfo(i); in resolveConflicts()
3315 VNInfo *VNI = LR.getValNumInfo(i); in pruneMainSegments()
3329 VNInfo *VNI = LR.getValNumInfo(i); in removeImplicitDefs()
3331 LR.removeValNo(VNI); in removeImplicitDefs()
3340 VNInfo *VNI = LR.getValNumInfo(i); in eraseInstrs()
3361 assert(I != LR.end()); in eraseInstrs()
3368 LR.removeValNo(VNI); in eraseInstrs()
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h104 LiveRange &LR; member
118 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
119 : LR(LR), DomNode(node), Kill(kill) {} in LiveInBlock()
130 bool isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
150 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
208 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
244 void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode,
246 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DLiveIntervals.h184 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
188 extendToIndices(LR, Indices, /*Undefs=*/{}); in extendToIndices()
198 void pruneValue(LiveRange &LR, SlotIndex Kill,
245 bool isLiveInToMBB(const LiveRange &LR, in isLiveInToMBB() argument
247 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
250 bool isLiveOutOfMBB(const LiveRange &LR, in isLiveOutOfMBB() argument
252 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
394 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
395 if (!LR) { in getRegUnit()
399 computeRegUnitRange(*LR, Unit); in getRegUnit()
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H A DLiveIntervalCalc.h39 void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
48 void createDeadDefs(LiveRange &LR, Register Reg);
54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { in extendToUses() argument
55 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
H A DLiveIntervalUnion.h114 const LiveRange *LR = nullptr; variable
125 Query(const LiveRange &LR, const LiveIntervalUnion &LIU) in Query() argument
126 : LiveUnion(&LIU), LR(&LR) {} in Query()
133 LR = &NewLR; in reset()
143 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion && in init()
/freebsd-13.1/contrib/llvm-project/llvm/lib/DebugInfo/GSYM/
H A DFunctionInfo.cpp158 LookupResult LR; in lookup() local
159 LR.LookupAddr = Addr; in lookup()
160 LR.FuncRange.Start = FuncAddr; in lookup()
173 if (LR.FuncRange.size() > 0 && !LR.FuncRange.contains(Addr)) in lookup()
225 SrcLoc.Name = LR.FuncName; in lookup()
227 LR.Locations.push_back(SrcLoc); in lookup()
228 return LR; in lookup()
238 SrcLoc.Name = LR.FuncName; in lookup()
243 LR.Locations.push_back(SrcLoc); in lookup()
246 return LR; in lookup()
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H A DLookupResult.cpp59 raw_ostream &llvm::gsym::operator<<(raw_ostream &OS, const LookupResult &LR) { in operator <<() argument
60 OS << HEX64(LR.LookupAddr) << ": "; in operator <<()
61 auto NumLocations = LR.Locations.size(); in operator <<()
68 OS << LR.Locations[I]; in operator <<()
H A DDwarfTransformer.cpp511 auto LR = Gsym->lookup(Addr); in verify() local
512 if (!LR) in verify()
513 return LR.takeError(); in verify()
530 NumDwarfInlineInfos != LR->Locations.size()) { in verify()
533 << LR->Locations.size() << "\n"; in verify()
540 Log << " " << LR->Locations.size() << " GSYM frames:\n"; in verify()
541 for (size_t Idx = 0, count = LR->Locations.size(); in verify()
543 const auto &gii = LR->Locations[Idx]; in verify()
552 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
554 const auto &gii = LR->Locations[Idx]; in verify()
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/freebsd-13.1/sys/arm/arm/
H A Ddb_trace.c83 state->registers[LR]); in db_stack_trace_cmd()
84 db_printsym(state->registers[LR], DB_STGY_PROC); in db_stack_trace_cmd()
91 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
148 state.registers[LR] = ctx->pcb_regs.sf_lr; in db_trace_thread()
168 state.registers[LR] = (uint32_t)__builtin_return_address(0); in db_trace_self()
H A Dstack_machdep.c63 state.registers[LR] = (uint32_t)__builtin_return_address(0); in stack_save()
83 state.registers[LR] = td->td_pcb->pcb_regs.sf_lr; in stack_save_td()
/freebsd-13.1/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DPointerSubChecker.cpp44 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
47 if (!(LR && RR)) in checkPreStmt()
50 const MemRegion *BaseLR = LR->getBaseRegion(); in checkPreStmt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp293 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR)); in getOrCreateFrameHelper()
298 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
306 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
320 .addReg(AArch64::LR); in getOrCreateFrameHelper()
330 .addUse(AArch64::LR) in getOrCreateFrameHelper()
341 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR); in getOrCreateFrameHelper()
366 if (std::find(Regs.begin(), Regs.end(), AArch64::LR) == Regs.end()) in shouldUseFrameHelper()
514 if (MO.getReg() == AArch64::LR) in lowerProlog()
531 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
543 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
H A DAArch64CallingConvention.td387 // end up saving LR as part of a call frame). Watch this space...
389 X25, X26, X27, X28, LR, FP,
398 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
399 // and not (LR,FP) pairs.
401 X25, X26, X27, X28, FP, LR,
414 X25, X26, X27, X28, LR, FP,
441 // register. Only X0 and LR are clobbered.
448 (sequence "X%u", 0, 28), FP, LR, SP,
485 // and LR (it is a call, after all) are preserved.
502 : CalleeSavedRegs<(add LR, FP)>;
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
288 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
304 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
310 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
318 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
322 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
331 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
342 // For most interrupts, all registers except SP and LR are shared with
345 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
348 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
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H A DThumb1FrameLowering.cpp225 case ARM::LR: in emitPrologue()
290 case ARM::LR: in emitPrologue()
576 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
693 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
730 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
783 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
953 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in restoreCalleeSavedRegisters()
1028 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
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H A DARMFrameLowering.cpp548 case ARM::LR: in emitPrologue()
768 case ARM::LR: in emitPrologue()
1279 Regs[0] = ARM::LR; in emitPopInst()
1838 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1895 if (Reg == ARM::LR) in determineCalleeSaves()
1903 case ARM::LR: in determineCalleeSaves()
1926 case ARM::LR: in determineCalleeSaves()
2204 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) && in determineCalleeSaves()
2692 .addReg(ARM::LR); in adjustForSegmentedStacks()
2698 .addReg(ARM::LR); in adjustForSegmentedStacks()
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