Lines Matching refs:LR
225 case ARM::LR: in emitPrologue()
290 case ARM::LR: in emitPrologue()
466 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) && in isCSRestore()
576 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
693 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
730 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
783 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters()
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
953 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in restoreCalleeSavedRegisters()
955 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in restoreCalleeSavedRegisters()
1028 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR)) in restoreCalleeSavedRegisters()
1031 if (Reg == ARM::LR) { in restoreCalleeSavedRegisters()