| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
62 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), in ArgFlagsTy()
73 bool isZExt() const { return IsZExt; } in isZExt()
74 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 506 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
509 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 279 bool IsZExt : 1; variable
296 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 310 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
3933 if (IsZExt) { in emiti1Ext()
4182 if (!IsZExt) { in emitLSR_ri()
4188 IsZExt = true; in emitLSR_ri()
4449 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4458 if (IsZExt) { in optimizeIntExtLoad()
4500 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4584 bool IsZExt = true; in selectMul() local
4590 IsZExt = true; in selectMul()
4654 IsZExt = true; in selectShift()
[all …]
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| H A D | AArch64ISelLowering.cpp | 3507 Entry.IsZExt = false; in LowerFSINCOS()
12305 bool IsZExt = false; in performVecReduceAddCombineWithUADDLP() local
12307 IsZExt = true; in performVecReduceAddCombineWithUADDLP()
12309 IsZExt = false; in performVecReduceAddCombineWithUADDLP()
12330 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
12341 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 169 unsigned DestReg, bool IsZExt);
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
924 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
926 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
1814 if (!IsZExt) { in PPCEmitIntExt()
1904 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
2310 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2317 IsZExt = true; in tryToFoldLoadIntoMI()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 190 bool IsZExt);
1757 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1758 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1895 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1903 if (IsZExt) in emitIntExt()
1982 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1983 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | BasicAliasAnalysis.cpp | 1174 bool IsZExt = DecompGEP1.VarIndices[i].ZExtBits > 0 || isa<ZExtInst>(V); in aliasGEP() local
1175 SignKnownZero |= IsZExt; in aliasGEP()
1176 SignKnownOne &= !IsZExt; in aliasGEP()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1995 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2147 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2156 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2241 Entry.IsZExt = false; in ExpandSinCosLibCall()
2249 Entry.IsZExt = false; in ExpandSinCosLibCall()
2257 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| H A D | FastISel.cpp | 1041 if (Arg.IsZExt) in lowerCallTo()
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| H A D | SelectionDAGBuilder.cpp | 9461 Entry.IsZExt = false; in LowerCallTo()
9562 if (Args[i].IsZExt) in LowerCallTo()
9641 else if (Args[i].IsZExt) in LowerCallTo()
9665 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | LegalizeIntegerTypes.cpp | 4057 Entry.IsZExt = false; in ExpandIntRes_XMULO()
4065 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | TargetLowering.cpp | 110 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
157 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
161 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 459 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9595 Entry.IsZExt = false; in LowerFSINCOS()
9605 Entry.IsZExt = false; in LowerFSINCOS()
19427 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28096 Entry.IsZExt = false; in LowerWin64_i128OP()
30068 Entry.IsZExt = false; in LowerFSINCOS()
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