Lines Matching refs:IsZExt
203 bool WantResult = true, bool IsZExt = false);
221 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
222 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
235 bool IsZExt = false);
239 bool IsZExt = false);
257 bool IsZExt = true);
260 bool IsZExt = true);
263 bool IsZExt = false);
303 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
310 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
1139 bool WantResult, bool IsZExt) { in emitAddSub() argument
1150 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
1154 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
1186 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1190 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue(); in emitAddSub()
1275 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1448 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) { in emitCmp() argument
1463 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1471 bool IsZExt) { in emitICmp() argument
1473 IsZExt) != 0; in emitICmp()
1515 bool SetFlags, bool WantResult, bool IsZExt) { in emitAdd() argument
1517 IsZExt); in emitAdd()
1544 bool SetFlags, bool WantResult, bool IsZExt) { in emitSub() argument
1546 IsZExt); in emitSub()
3834 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
3835 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
3925 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext() argument
3933 if (IsZExt) { in emiti1Ext()
4017 uint64_t Shift, bool IsZExt) { in emitLSL_ri() argument
4042 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4081 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri()
4120 uint64_t Shift, bool IsZExt) { in emitLSR_ri() argument
4145 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4177 if (Shift >= SrcBits && IsZExt) in emitLSR_ri()
4182 if (!IsZExt) { in emitLSR_ri()
4183 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4188 IsZExt = true; in emitLSR_ri()
4197 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri()
4236 uint64_t Shift, bool IsZExt) { in emitASR_ri() argument
4261 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4293 if (Shift >= SrcBits && IsZExt) in emitASR_ri()
4302 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri()
4316 bool IsZExt) { in emitIntExt() argument
4336 return emiti1Ext(SrcReg, DestVT, IsZExt); in emitIntExt()
4339 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4341 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4346 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4348 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4353 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4441 bool IsZExt = isa<ZExtInst>(I); in optimizeIntExtLoad() local
4449 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4458 if (IsZExt) { in optimizeIntExtLoad()
4498 bool IsZExt = isa<ZExtInst>(I); in selectIntExt() local
4500 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4516 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4584 bool IsZExt = true; in selectMul() local
4590 IsZExt = true; in selectMul()
4599 IsZExt = false; in selectMul()
4610 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4647 bool IsZExt = I->getOpcode() != Instruction::AShr; in selectShift() local
4654 IsZExt = true; in selectShift()
4663 IsZExt = false; in selectShift()
4676 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4679 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4682 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()