| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemProfiler.cpp | 150 bool IsWrite; member
178 bool IsWrite);
336 Access.IsWrite = false; in isInterestingMemoryAccess()
343 Access.IsWrite = true; in isInterestingMemoryAccess()
351 Access.IsWrite = true; in isInterestingMemoryAccess()
359 Access.IsWrite = true; in isInterestingMemoryAccess()
374 Access.IsWrite = true; in isInterestingMemoryAccess()
378 Access.IsWrite = false; in isInterestingMemoryAccess()
445 IsWrite); in instrumentMaskedLoadOrStore()
451 if (Access.IsWrite) in instrumentMop()
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| H A D | ThreadSanitizer.cpp | 480 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
481 Value *Addr = IsWrite ? cast<StoreInst>(I)->getPointerOperand() in chooseInstructionsToInstrument()
487 if (!IsWrite) { in chooseInstructionsToInstrument()
522 if (IsWrite) { in chooseInstructionsToInstrument()
644 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
658 if (IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
676 if (!IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
700 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
705 OnAccessFunc = IsWrite ? TsanUnalignedVolatileWrite[Idx] in instrumentLoadOrStore()
711 if (IsCompoundRW || IsWrite) in instrumentLoadOrStore()
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| H A D | AddressSanitizer.cpp | 1465 bool IsWrite = F->getName().startswith("llvm.masked.store."); in getInterestingMemoryOperands() local
1467 unsigned OpOffset = IsWrite ? 1 : 0; in getInterestingMemoryOperands()
1468 if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads) in getInterestingMemoryOperands()
1550 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress() argument
1642 if (O.IsWrite) in instrumentMop()
1651 O.IsWrite, nullptr, UseCalls, Exp); in instrumentMop()
1669 Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][0], in generateCrashCode()
1672 Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][1], in generateCrashCode()
1707 uint32_t TypeSize, bool IsWrite, Value *SizeArgument) { in instrumentAMDGPUAddress() argument
1805 IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][0], in instrumentUnusualSizeOrAlignment()
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| H A D | HWAddressSanitizer.cpp | 253 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
812 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
821 (IsWrite << HWASanAccessInfo::IsWriteShift) + in instrumentMemAccessInline()
944 IRB.CreateCall(HwasanMemoryAccessCallback[O.IsWrite][AccessSizeIndex], in instrumentMemAccess()
947 instrumentMemAccessInline(Addr, O.IsWrite, AccessSizeIndex, O.getInsn()); in instrumentMemAccess()
950 IRB.CreateCall(HwasanMemoryAccessCallbackSized[O.IsWrite], in instrumentMemAccess()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Transforms/Instrumentation/ |
| H A D | AddressSanitizerCommon.h | 28 bool IsWrite; variable
35 InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
38 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() argument
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 703 bool IsWrite = Access.getInt(); in createCheckForAccess() local
704 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in createCheckForAccess()
744 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
746 if (IsWrite) in canCheckPtrAtRT()
750 AccessInfos.emplace_back(Ptr, IsWrite); in canCheckPtrAtRT()
905 bool IsWrite = AC.getInt(); in processMemAccesses() local
909 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
914 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
918 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
935 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /freebsd-13.1/contrib/llvm-project/compiler-rt/lib/tsan/rtl/ |
| H A D | tsan_rtl.h | 204 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
254 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
283 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
291 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
299 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| H A D | tsan_rtl_report.cpp | 185 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4188 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in lowerPREFETCH() local
4189 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3236 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); in LowerPREFETCH() local
3252 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
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