658                          Value *Addr, uint32_t TypeSize, bool IsWrite,
662                                        uint32_t TypeSize, bool IsWrite,
666                                         uint32_t TypeSize, bool IsWrite,
672                                  bool IsWrite, size_t AccessSizeIndex,
1465       bool IsWrite = F->getName().startswith("llvm.masked.store.");  in getInterestingMemoryOperands()  local
1467       unsigned OpOffset = IsWrite ? 1 : 0;  in getInterestingMemoryOperands()
1468       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1480       Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, Mask);  in getInterestingMemoryOperands()
1550                                 uint32_t TypeSize, bool IsWrite,  in doInstrumentAddress()  argument
1558     return Pass->instrumentAddress(I, InsertBefore, Addr, TypeSize, IsWrite,  in doInstrumentAddress()
1561                                          IsWrite, nullptr, UseCalls, Exp);  in doInstrumentAddress()
1569                                         bool IsWrite, Value *SizeArgument,  in instrumentMaskedLoadOrStore()  argument
1599                         Granularity, ElemTypeSize, IsWrite, SizeArgument,  in instrumentMaskedLoadOrStore()
1642   if (O.IsWrite)  in instrumentMop()
1651                                 O.IsWrite, nullptr, UseCalls, Exp);  in instrumentMop()
1654                         Granularity, O.TypeSize, O.IsWrite, nullptr, UseCalls,  in instrumentMop()
1660                                                  Value *Addr, bool IsWrite,  in generateCrashCode()  argument
1669       Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][0],  in generateCrashCode()
1672       Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][1],  in generateCrashCode()
1677           IRB.CreateCall(AsanErrorCallback[IsWrite][0][AccessSizeIndex], Addr);  in generateCrashCode()
1679       Call = IRB.CreateCall(AsanErrorCallback[IsWrite][1][AccessSizeIndex],  in generateCrashCode()
1707     uint32_t TypeSize, bool IsWrite, Value *SizeArgument) {  in instrumentAMDGPUAddress()  argument
1730                                          uint32_t TypeSize, bool IsWrite,  in instrumentAddress()  argument
1735                                            TypeSize, IsWrite, SizeArgument);  in instrumentAddress()
1746       IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],  in instrumentAddress()
1749       IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],  in instrumentAddress()
1788   Instruction *Crash = generateCrashCode(CrashTerm, AddrLong, IsWrite,  in instrumentAddress()
1799     bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) {  in instrumentUnusualSizeOrAlignment()  argument
1805       IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][0],  in instrumentUnusualSizeOrAlignment()
1808       IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][1],  in instrumentUnusualSizeOrAlignment()
1814     instrumentAddress(I, InsertBefore, Addr, 8, IsWrite, Size, false, Exp);  in instrumentUnusualSizeOrAlignment()
1815     instrumentAddress(I, InsertBefore, LastByte, 8, IsWrite, Size, false, Exp);  in instrumentUnusualSizeOrAlignment()