| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IVDescriptors.cpp | 508 RecurrenceDescriptor::InstDesc
525 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
545 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
557 RecurrenceDescriptor::InstDesc
561 return InstDesc(false, I); in isConditionalRdxPattern()
566 return InstDesc(false, I); in isConditionalRdxPattern()
574 return InstDesc(false, I); in isConditionalRdxPattern()
580 return InstDesc(false, I); in isConditionalRdxPattern()
591 return InstDesc(false, I); in isConditionalRdxPattern()
594 RecurrenceDescriptor::InstDesc
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | IVDescriptors.h | 82 class InstDesc {
84 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
88 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
119 static InstDesc isRecurrenceInstr(Instruction *I, RecurKind Kind,
120 InstDesc &Prev, FastMathFlags FMF);
134 static InstDesc isMinMaxSelectCmpPattern(Instruction *I,
135 const InstDesc &Prev);
139 static InstDesc isConditionalRdxPattern(RecurKind Kind, Instruction *I);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst() argument
223 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); in shouldReplaceInst()
228 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
256 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 60 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,
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| H A D | ARMMCTargetDesc.cpp | 198 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget() argument
203 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; in evaluateBranchTarget()
210 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 450 const MCInstrDesc &InstDesc = MI->getDesc(); in tryAddToFoldList() local
451 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo]; in tryAddToFoldList()
459 for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) { in tryAddToFoldList()
1574 const MCInstrDesc &InstDesc = UseMI->getDesc(); in tryFoldRegSequence() local
1575 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in tryFoldRegSequence()
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| H A D | SIInstrInfo.cpp | 3483 const MCInstrDesc &InstDesc = MI.getDesc(); in isImmOperandLegal() local
3484 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo]; in isImmOperandLegal()
3505 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo)) in isImmOperandLegal()
4701 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
4702 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
4725 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) { in isOperandLegal()
4734 isLiteralConstantLike(Op, InstDesc.OpInfo[i])) { in isOperandLegal()
6404 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
6534 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
6560 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 435 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode()); in isMacroFused() local
436 if (!InstDesc.isConditionalBranch()) in isMacroFused()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1971 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand() local
1974 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1977 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1978 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); in addLiteralImmOperand()
1983 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType; in addLiteralImmOperand()
2000 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
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