3483   const MCInstrDesc &InstDesc = MI.getDesc();  in isImmOperandLegal()  local
3484   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];  in isImmOperandLegal()
3505   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))  in isImmOperandLegal()
4701   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
4702   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];  in isOperandLegal()
4725             usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {  in isOperandLegal()
4730       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {  in isOperandLegal()
4733       } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&  in isOperandLegal()
4734                  isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {  in isOperandLegal()
6404   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
6419   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);  in splitScalar64BitUnaryOp()
6425   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
6534   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
6560   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
6565   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
6638   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
6653   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);  in splitScalar64BitBCNT()
6655   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);  in splitScalar64BitBCNT()