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Searched refs:FP_TO_SINT (Results 1 – 25 of 36) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1032 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
1033 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
1034 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
1040 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
1041 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
1042 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
1048 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
1049 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
1064 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
1065 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp450 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
451 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
892 setTargetDAGCombine(ISD::FP_TO_SINT); in AArch64TargetLowering()
1161 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in AArch64TargetLowering()
1454 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
1544 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForFixedLengthSVE()
4873 case ISD::FP_TO_SINT: in LowerOperation()
12869 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in performFpToIntCombine()
16617 case ISD::FP_TO_SINT: in PerformDAGCombine()
17286 case ISD::FP_TO_SINT: in ReplaceNodeResults()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1576 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
1577 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
1693 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, in getCastInstrCost()
1694 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, in getCastInstrCost()
1695 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, in getCastInstrCost()
1696 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, in getCastInstrCost()
1697 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, in getCastInstrCost()
1698 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, in getCastInstrCost()
1699 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, in getCastInstrCost()
1700 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp265 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom); in X86TargetLowering()
849 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1024 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
1699 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal); in X86TargetLowering()
1839 setOperationAction(ISD::FP_TO_SINT, VT, in X86TargetLowering()
21326 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
21714 FpToIntOpcode = ISD::FP_TO_SINT; in LowerFP_TO_INT_SAT()
28420 return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt); in convertShiftLeftToScale()
30479 case ISD::FP_TO_SINT: in LowerOperation()
30882 case ISD::FP_TO_SINT: in ReplaceNodeResults()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp634 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
667 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
669 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
671 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
673 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
675 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
677 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
679 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, in getCastInstrCost()
681 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, in getCastInstrCost()
683 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp174 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
301 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
965 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
1039 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1041 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
5785 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
9362 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
10141 case ISD::FP_TO_SINT: in LowerOperation()
15896 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h785 FP_TO_SINT, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp404 case ISD::FP_TO_SINT: in LegalizeOp()
584 case ISD::FP_TO_SINT: in Promote()
689 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
690 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp828 case ISD::FP_TO_SINT: in SoftenFloatOperand()
944 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
1778 case ISD::FP_TO_SINT: in ExpandFloatOperand()
1910 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2087 case ISD::FP_TO_SINT: in PromoteFloatOperand()
2883 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp352 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeDAG.cpp2563 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2579 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2923 case ISD::FP_TO_SINT: in ExpandNode()
4192 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
4198 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
4431 case ISD::FP_TO_SINT: in PromoteNode()
H A DLegalizeVectorTypes.cpp95 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
611 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
990 case ISD::FP_TO_SINT: in SplitVectorResult()
2198 case ISD::FP_TO_SINT: in SplitVectorOperand()
3095 case ISD::FP_TO_SINT: in WidenVectorResult()
4561 case ISD::FP_TO_SINT: in WidenVectorOperand()
H A DTargetLowering.cpp6771 ISD::FP_TO_SINT; in expandFP_TO_UINT()
6789 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
6836 SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val); in expandFP_TO_UINT()
6845 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
6847 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, in expandFP_TO_UINT()
8716 SDValue FpToInt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, in expandFP_TO_INT_SAT()
8737 DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); in expandFP_TO_INT_SAT()
H A DLegalizeIntegerTypes.cpp131 case ISD::FP_TO_SINT: in PromoteIntegerResult()
600 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
601 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
2118 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
H A DFastISel.cpp1786 return selectCast(I, ISD::FP_TO_SINT); in selectOperator()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp139 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom); in R600TargetLowering()
140 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
250 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
646 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1774 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp443 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
464 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
1307 case ISD::FP_TO_SINT: in LowerOperation()
1735 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2690 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
2836 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
2841 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp258 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
491 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
501 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
642 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
683 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
7989 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in convertFPToInt()
8036 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INTForReuse()
8093 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
10956 case ISD::FP_TO_SINT: in ReplaceNodeResults()
13724 Opcode = ISD::FP_TO_SINT; in combineElementTruncationToVectorTruncation()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1513 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1515 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3030 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3357 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3363 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp373 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in RISCVTargetLowering()
480 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
516 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
700 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
2379 case ISD::FP_TO_SINT: in LowerOperation()
2450 case ISD::FP_TO_SINT: in LowerOperation()
4879 case ISD::FP_TO_SINT: in ReplaceNodeResults()
4884 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp358 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1232 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2779 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()
H A DMipsSEISelLowering.cpp356 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); in addMSAIntType()
1932 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1770 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1771 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1772 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1810 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()

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